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  • I am an FPGA SoC engineer and I want to create a custom SoC. Is it possible for me to learn and acquire the development flow for less than 5K EUR budget – and if so, how should I proceed?

    This question was raised in the ‘Want to maximise your product design? See how a custom ASIC can help?' webinar, view all the questions in the round-up blog post.

  • ‘Low cost’ is a benefit of custom SoCs. At what quantities do the low-cost benefits start to come in, relative to, for example, digital/analog designs based upon off-the-shelf devices?

    This question was raised in the ‘Want to maximise your product design? See how a custom ASIC can help?' webinar, view all the questions in the round-up blog post.

  • With regards to custom SoCs, what is the trade-off between low cost and performance?

    This question was raised in the ‘Want to maximise your product design? See how a custom ASIC can help?' webinar, view all the questions in the round-up blog post.

  • Is it possible to interface a high frequency sensor-signal output from an analog ASIC chip (e.g. several Kilohertz) using Cortex-M?

    This question was raised in the ‘Want to maximise your product design? See how a custom ASIC can help?' webinar, view all the questions in the round-up blog post.

  • Can SoC Verification be automated using Machine Learning? If so, how can we ensure 100% functional coverage?

    This question was raised in the ‘Want to maximise your product design? See how a custom ASIC can help?' webinar, view all the questions in the round-up blog post.

  • How is the SoC-based design validated? Is it done against some specifications or compliance?

    This question was raised in the ‘Want to maximise your product design? See how a custom ASIC can help?' webinar, view all the questions in the round-up blog post.

  • Assuming knowledge of standard off-the-shelf SoC and FPGA designs, what big challenges exists for an integrated solution?

    This question was raised in the ‘Want to maximise your product design? See how a custom ASIC can help?' webinar, view all the questions in the round-up blog post.

  • Is the DesignStart Eval compatible with heterogeneous multi-core design, e.g. Cortex-M0 with Cortex-M3?

    This question was raised in the webinar "Enhance your product with industry-leading processors - for no upfront license fee.”

  • Could you recommend a specific FPGA board for ARM Cortex-M0 and Cortex-M3 implementation?

    This question was raised in the webinar "Enhance your product with industry-leading processors - for no upfront license fee.”

  • Are DesignStart Pro royalties based on the number of cores instantiated in single chip? If so, what about permanent lockstep configurations?

    This question was raised in the webinar "Enhance your product with industry-leading processors - for no upfront license fee.”

  • If I am an individual how can I apply for the DesignStart program and get a prototype?

    This question was raised in the webinar "Enhance your product with industry-leading processors - for no upfront license fee.”

  • Fab costs prohibit many start-ups and small companies to pursue custom SoC development. Does ARM have any plans to help companies on this, maybe with some fab partners similar to the design partners

    This question was raised in the webinar "Enhance your product with industry-leading processors - for no upfront license fee.”

  • Can the DesignStart Eval RTL project provided be modified? For example, to add new ports or remove unused ones for customization.

    This question was raised in the webinar "Enhance your product with industry-leading processors - for no upfront license fee.”

  • Is there any documentation for design implementation on ARM Keil software?

    This question was raised in the webinar "Enhance your product with industry-leading processors - for no upfront license fee.”

  • What ASIL level can be achieved with the Cortex-M3 processor?

    This question was raised in the webinar "Enhance your product with industry-leading processors - for no upfront license fee.”

  • For IoT implementation, which is better: the Cortex-M0 or Cortex-M3 - and why?

    This question was raised in the webinar "Enhance your product with industry-leading processors - for no upfront license fee.”

  • We are looking to build a new FPU.  Can we get hooks to build this FPU into the SoC?

    This question was raised in the webinar "Enhance your product with industry-leading processors - for no upfront license fee.”

  • What are the approximate numbers for gates required for a Cortex-M0 and Cortex-M3 CPU?

    This question was raised in the webinar "Enhance your product with industry-leading processors - for no upfront license fee.”

  • Will there be tutorials, videos that explain more details on the design process? Is there a possibility of simulation/test for effectiveness?

    This question was raised in the webinar "Enhance your product with industry-leading processors - for no upfront license fee.”

  • Does the Cortex-M0 include any security options?

    This question was raised in the webinar "Enhance your product with industry-leading processors - for no upfront license fee.”

  • Are the CoreSight Debug components made available through DesignStart also?

    This question was raised in the webinar "Enhance your product with industry-leading processors - for no upfront license fee.”

  • What is the maximum running frequency for Cortex-M3 on TSMC 40nm process?

    This question was raised in the webinar "Enhance your product with industry-leading processors - for no upfront license fee.”

  • The Cortex-M0 and Cortex-M3 processors are free for FPGA prototyping, but are they also free for IC prototyping?

    This question was raised in the webinar "Enhance your product with industry-leading processors - for no upfront license fee.”

  • How to implement Cortex-M3 DesignStart Eval r0p0-02rel0 to Xilinx virtex 5 board?

    Hi.

    I came across Cortex-M3 DesignStart Eval r0p0-02rel0 implementing to the boards name of  ALTERA's MPS2+ from here https://developer.arm.com/products/system-design/development-boards/cortex-m-prototyping-system .

    But I'm looking for Xilinx board…

  • CMSDK - design multi-master bus

     asked: "with the M3 designstart CMSDK, is it possible to design multi-master bus? In the IoT Cortex-M TRM, only an ahb-lite structure is illustrated. That document does mention AHB and APB expansion through INTEXP[1:0] but what if there are more…