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  • Cortex-M0 DesignStart processor size (FPGA)?

    Dear sirs,

    I have a question about the size of synthesized logic for Cortex-M0 DesignStart processor.

    When I use ISE of Xilinx to synthesize Cortex-M0 DesignStart processor (version r1p0-00rel0), I have result as below.

    (I configure for using Spartan…

  • Cortex- M1/M0 softcore

    Hi all,

    My main goal is to rebuild the core and the peripherals of an STM32F0xx into an FPGA. An idea to realize this is to use a softcore and build up the used peripherals by connecting them to the supported BUS system.

    As far as I understand is the…

  • Why is SoC Design so hard?

    The exploding IoT (Internet of Things) chip market is expected to reach 20 billion devices by 2020 by many predictions. The majority of these will NOT be wearables. 

     

    The IoT market will be driven by Data and Subscription business models. THOUSANDS of…