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  • First compile, verilog files missing

    Hi,

    I am just performing the first steps with the DesignStart Eval Edition (Cortex-M0), trying to compile the verilog sources to get a simulation running.

    So I changed /systems/fpga_testbench/trl_sim/makefile to use gcc and modelsim and now I want to …

  • Cortex-M0 example system

    Hi,

    II refer to the example MCU system level in the document "arm_cortex_m0_designstart_eval_user_guide", put it into MPS2+ after synthesis, the software uses the following example in this directory.

    D:\CMPS3\AT510-MN-80001-r2p0-00rel0\systems…

  • How to load program into DesingStart SoC

    Hi,

    I am trying to get familiarize with the SoC design provided with Desgin Start Cortex-M0 Eval version.

    Here is my setup:

    1. ARM Cortex-M0 core
    2. Design Start Eval  with CMSDK used for SOC design.
    3. Keil MDK – mdk_pro uvision V5.25.2.0
    4. Vivado Tool used…