Hi,
I want to simulate CM3 Designstart with Modelsim.
When I launch Modelsim from Quartus 17.2 most of the files compile. But I get the following error:
** Error: C:/projects/AT421-MN-80001-r0p0-02rel0/smm/logical/smm_common_fpga/verilog/fpga_pll_speed…