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  • I am an FPGA SoC engineer and I want to create a custom SoC. Is it possible for me to learn and acquire the development flow for less than 5K EUR budget – and if so, how should I proceed?

    This question was raised in the ‘Want to maximise your product design? See how a custom ASIC can help?' webinar, view all the questions in the round-up blog post.

  • ‘Low cost’ is a benefit of custom SoCs. At what quantities do the low-cost benefits start to come in, relative to, for example, digital/analog designs based upon off-the-shelf devices?

    This question was raised in the ‘Want to maximise your product design? See how a custom ASIC can help?' webinar, view all the questions in the round-up blog post.

  • With regards to custom SoCs, what is the trade-off between low cost and performance?

    This question was raised in the ‘Want to maximise your product design? See how a custom ASIC can help?' webinar, view all the questions in the round-up blog post.

  • Is it possible to interface a high frequency sensor-signal output from an analog ASIC chip (e.g. several Kilohertz) using Cortex-M?

    This question was raised in the ‘Want to maximise your product design? See how a custom ASIC can help?' webinar, view all the questions in the round-up blog post.

  • Can SoC Verification be automated using Machine Learning? If so, how can we ensure 100% functional coverage?

    This question was raised in the ‘Want to maximise your product design? See how a custom ASIC can help?' webinar, view all the questions in the round-up blog post.

  • How is the SoC-based design validated? Is it done against some specifications or compliance?

    This question was raised in the ‘Want to maximise your product design? See how a custom ASIC can help?' webinar, view all the questions in the round-up blog post.

  • Assuming knowledge of standard off-the-shelf SoC and FPGA designs, what big challenges exists for an integrated solution?

    This question was raised in the ‘Want to maximise your product design? See how a custom ASIC can help?' webinar, view all the questions in the round-up blog post.

  • What is the maximum running frequency for Cortex-M3 on TSMC 40nm process?

    This question was raised in the webinar "Enhance your product with industry-leading processors - for no upfront license fee.”

  • First compile, verilog files missing

    Hi,

    I am just performing the first steps with the DesignStart Eval Edition (Cortex-M0), trying to compile the verilog sources to get a simulation running.

    So I changed /systems/fpga_testbench/trl_sim/makefile to use gcc and modelsim and now I want to …

  • External BRAM as I/D memory for Cortex-M1 DesignStart package for Xilinx FPGAs

    Hi,

    I'd like to try and use external BRAM as the I/D memory for the Cortex-M1 DesignStart package for Xilinx FPGAs. The reference examples for Arty boards use the internal TCMs.

    I've built a design in Vivado with a BRAM connected to the AXI3 port mapped…

  • FreeRTOS, Peripheral Modules with DesignStart FPGA

    Hello all,

    I have 2 questions regarding the Cortex M IP cores for Xilinx FPGAs (M1 on the Arty A7/S7, provided by ARM)

    1) I am new to ARM DesignStart and am looking to use freeRTOS with the Cortex M1 which project which has been provided for the Arty A7…

  • Cortex M3 on Arty A35T with Vivado 2018.3 Windows 10

    Hi. First of all, thanks for your attention in advance. I have to say that I am completely new in FPGA programming, but I could have never imagined that running an example with a documentation explaining it step by step could be so cumbersome and error…

  • Cortex-M1 for Xilinx FPGAs, max. clock frequency?

    Hello,

    I have already played around with the Cortex-M1 reference designs for Xilinx Spartan and Artix boards, can you give an indication of what your maximum target frequency for the processor IP core is? Are the referenced 100 MHz a good design practice…