Arm Cycle Model Studio (CMS) is a useful tool to create SystemC simulation models from Verilog RTL source code. SystemC models that are created with CMS run well with a variety of simulators and are easy to share with others inside and outside of a company…
我在用ARM Cycle Model Studio工具想把RTL代码转成SystemC代码，我进行了相关设置（编译选项和输入的file list）之后，然后点击了编译，发现编译是能通过的，但是生成的generated file里面的.clock和.cycle文件都是空的，想问一下，一般情况下这两个文件是怎么生成的？空的原因可能是什么？
PS：RTL代码是时序逻辑的代码，CMS版本9.4.0