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  • Measuring Cortex-M4 instruction clock cycle counts

    I'm trying to find a reliable method for measuring instruction clock cycles on the STM32F429 MCU that incorporates a Cortex-M4 processor. Part of the challenge is that although the core CPU has no cache, ST added their own proprietary ART Accelerator…

  • How does Cortex-m4 core interact with other master devices?

    How does Cortex-m4 interacts with other master devices such as DMA while m4 core does not have Hbusreq and Hgrant ports? m4 core does not have interfaces to arbiter.

  • Raising priority of PendSV within NVIC when PendSV pending

    Hi,

    I'm trying to understand the behavior of raising (lowering numerical priority) the priority of PendSV in the NVIC of a Cortex M4 or M7 when PendSV is already pending. Below are the cases I'm grappling with,

    1) High priority interrupt ISR is…

  • Webinar: Secure Bootloader Design Techniques for MCUs

    September 26, 2018 05:00 PM to 06:00 PM Coordinated Universal Time
    Online
    A major challenge facing embedded software engineers today is designing and implementing a secure bootloader solution. Secure bootloaders require specialized knowledge in disparate disciplines such as driver software, middleware, cryptography, security...
  • Webinar: Secure Bootloader Design Techniques for MCUs

    September 26, 2018 10:00 AM to 11:00 AM Coordinated Universal Time
    Online
    A major challenge facing embedded software engineers today is designing and implementing a secure bootloader solution. Secure bootloaders require specialized knowledge in disparate disciplines such as driver software, middleware, cryptography, security...
  • Interruptible Instructions on Cortex-M4

    The ARM Cortex-M4 Processor Technical Reference Manual states:

    To minimize interrupt latency, the processor abandons any divide instruction to take any pending interrupt. On return from the interrupt handler, the processor restarts the divide instruction…

  • What is the top level difference in features between Cortex-M33 and Cortex-M4?

    This is a very common question.

    The diagram below is a pictorial description of the differences followed by some explanations.

    Cortex-M33 v Cortex-M4 features

    Starting from the bottom:

    • Cortex-M33 is an implementation of the ARMv8-M architecture. Full details are in my blog on the 5…
  • Implementing Embedded Continuous Integration with Jenkins and Docker: Part 1

    This blog is part one in a three-part series. Part two and part three will be linked here when available. 

    Introduction

    Imagine a software development world where:

    • nasty merge conflicts rarely (if ever) occur.
    • the code in version control always works…
  • Which ARM development board should I use for audio DSP with ARM Cortex-M4?

    Hi experts.

    I am somehow new in ARM. Can anybody pls help me on choosing an appropriate cheap board for learning DSP with ARM cortex-M4?

  • LDREX/STREX on the M3,M4,M7

    Doing some research of the LDREX and STREX it appears that the exclusivity address range for these instructions on the M3,M4,M7 is the entire memory space. Hence you can only use the LDREX/STREX with one address.   Does this not limit you to one Mutex …

  • How to prepare ADC data for Q31_t CMSIS DSP functions?

    Hi to you all,
    I've another post on the forum (here's the link Process ADC data, moved by DMA, using CMSIS DSP: what's the right way? ), but since I think I made some small steps forward I felt I could be a little more specific. I hope this…

  • Cortex-M4汇编函数参数传递

    ARM Cortex-M4处理器在C源文件里面调用汇编函数,参数传递机制是怎样的?

    比如C源文件里面调用汇编语言实现的函数uint8_t Code(uint8_t a,uint32_t b,uint8_t *p)之后,参数a、b、c将被传递到内核Cortex-M4中哪几个寄存器中执行?有没有相关文档进行了详细说明?谢谢

  • what situation will the FPCA in Cortex-M4 change?

    Hi all,

    I'm study Cortex-M4 recently, and try to use floating point calculation,

    I read the book about that saying FPCA in control register will be set 1 after FPU work,

    but I'm not sure that when will FPCA be changed after set 1, or it will never…

  • M4 Assembly - Set Enable also enables the Clear Enable Interrupt Register

    Hi,

    I have some assembly for Cortex M4 (Arm 7M Thumb), I want to enable an interrupt that is connected to a push button on an STM32 F407. It works, but for some reason when I enable the set enable register, the clear enable register also gets set ? Is…

  • Does Cortex-M3/M4 continue with burst in response to ERROR?

    AMBA spec states that 'Master can choose whether to terminate current burst or continue with burst in response to ERROR'.
    What does Cortex-M3/M4 do in response to ERROR? Does it continue with burst in response to ERROR in some special cases?

  • Cortex M4 - Returning from Interrupt

    Hi,

    I'm using the STM32 F407 (Cortex M4), and I am also only using assembly in uVision IDE. So far I have managed to setup a ISR for a pushbutton generated interrupt via GPIO. This all works, I get the ISR handler hit, but after I perform my ISR function…

  • An algorithm on a M7 is slower than on M4 - why?

    Hi there,

    we are working on an audio project, where we move some firmware from an STM32F407 (ARM Cortex M4) to an ATSAME70 (ARM Cortex M7). Despite the ATSAME70 runing at 300 MHz, while the STM32F407 runs at only 168 MHz, the ATSAME70 is definitely slower…

  • Teaching Scratchy to Walk with Neural Networks

    What would you do with a Cortex-M4, a motor or two, some lego and a few cable ties? Well, if you’re Sebastian Förster, an embedded systems developer based in Germany, the answer is a small, four-legged robot that you’d teach to walk using neural networks…

  • Explanation of cycles on pre and post index-addressing in case of Load and Store instructions.

    Hello to all,

    I am working on Cortex-M4 and in order to implement the load and store instructions, I have chosen the pre and post-index addressing and the memory arrangement is little endian. Therefore during the execution, an observation related to consumed…

  • Is offset of 30 in load and store instructions shows an exceptional case?

    Hello to all,

    I am working on ARM Cortex-M4 and the memory arrangement is the little endian. I have started working on the memory instructions and for that purpose, I have chosen the offset addressing and the relationship between the offset and cycles…

  • MPU is not triggering MemFault or HardFault

    MPU is not triggering MemManage fault. I want to protect a memory region of 64 bytes starting from 0x20000000. I've configured the MPU registers accordingly, but when I write in a protected memory location, MPU does not trigger fault.

    Here's a code…

  • What happens when offset value becomes 30 in case of load/store operation

    Hello to all,

    I was looking at different offset values for both load and store operations. Since due to little endian arrangement, the memory looks something like this to processor:

    Byte[0x23],Byte[0x22],Byte[0x21],Byte[0x20]

    Byte[0x1F],Byte[0x1E],Byte…

  • Cortex-M4 Suspend/Resume Interrupts

    Hi together,

    im am working on a project managing high IRQ/ISR loads. (NXP S32K14x)

    On some critical sections i have to suspend global interrupt mechanism (cpsid i) and resume afterwards.

    Is it necessary to include a _dsb or _isb instruction after disabling…

  • My application seems to be dropping interrupts; does returning from an interrupt clear its pending flag?

    I'm working with a Cortex M4 (Freescale's Freedom-K64F dev-board). I'm trying to write a long sequence of data to flash. The state machine for this sequence operates in the interrupt handler. This means that in the handler for the processor's flash-controller…

  • How the current consumption is affected by instruction address

    Hello to all,

    I am willing to know the variation in the current consumption due to the instruction address. Therefore I have performed two experiments, first time filled the pipeline with a 32-bit instruction and second time filled it with the 16-bit…