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  • about tail chaning of Cortex-M0

    Hello.

    I'm studying about the tail chaining of Cortex-M0.

    Is it same as Cortex-M3 or M4?

    Best regards.

  • cmsis NVIC question.

    Hello, Everybody. I have several questions.

    1. Please See the NVIC_Type structure. I don't understand about why ISER,ICER,ISPR and ICPR use size of array 1( I think It can use just __IO uint32_t ISER; ), and what does RESERVEDs do???

    2. I would like…

  • coming from AVR 8-bitter,starting ARM CORTEX-M programming

    Hi everyone, as I wrote in the title, I'm coming from AVR 8-bit MCUs programming and in the last year I learnt a lot about AVR 8-bit architecture,CPU,registers and so on.

    I've done a few projects coding primarily in C and something in Assembly (serial…

  • How long bitfields on which ARM?

    I need to be able to handle long bitfields as effectively as possible. Right now I need up to 64 bits in length.

    Are there instructions to set, clear and test individual bits in one cycle available for some of the architectures? Which? Particularly, will…

  • How to get Cortex m3 soft core

    Hi,

    I needed to know where i could get arm cortex m3 soft core. Its for my masters thesis for which i'll be also using Keil uvision 5.

    Thanks in advance

  • Debugging a Cortex-M0 Hard Fault

  • Where to find the execution cycles of Cortex m7 instruction

    for Cortex-M0, M3 and M4, I can find the execution time in their Technical Reference Manual > Programmers Model > Instruction set summary 里面查看

    http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0432c/CHDCICDF.html

    but for M7 It said that…

  • How to use compiled Hex file from Keil on windows to the design_start?

    Hi,

    Thanks for your supporting in advance, As I know M0 or M3's design start kit have some example which is firmware such as Hello.

    If I compiled that Hello firmware in the window, then can I use directly into the design start kit? or should I need…

  • M0+ Stack Pointer (PSP/MSP) Clarification

    Background

     I'm working part-time on a Cortex M0+ based SoC converting a very processor-intensive section of C++ code (inner-loop executed 10s of 1000s of times a second & compiles to over 400 instructions using GNU O3) and after almost 3 months of work…

  • V2M MPS2+: 'ERROR: FPGA did not configure.'

    Hi all,

    We have purchased an MPS2+ platform, and everything was going well, but since Friday we are facing an error we do not understand.

    When starting the FPGA configuration (by pressing the 'ON' button on the board), leds start blinking (the screen…

  • What is the top level difference in features between Cortex-M23 and Cortex-M0+?

    This is a very common question too.

    The diagram is a pictorial description of the differences followed by some explanations.

     

     

    Starting from the bottom:

     

    -Cortex-M23 is an implementation of the ARMv8-M architecture. Full details here.

    -Using the same debug…

  • I am an FPGA SoC engineer and I want to create a custom SoC. Is it possible for me to learn and acquire the development flow for less than 5K EUR budget – and if so, how should I proceed?

    This question was raised in the ‘Want to maximise your product design? See how a custom ASIC can help?' webinar, view all the questions in the round-up blog post.

  • ‘Low cost’ is a benefit of custom SoCs. At what quantities do the low-cost benefits start to come in, relative to, for example, digital/analog designs based upon off-the-shelf devices?

    This question was raised in the ‘Want to maximise your product design? See how a custom ASIC can help?' webinar, view all the questions in the round-up blog post.

  • With regards to custom SoCs, what is the trade-off between low cost and performance?

    This question was raised in the ‘Want to maximise your product design? See how a custom ASIC can help?' webinar, view all the questions in the round-up blog post.

  • Is it possible to interface a high frequency sensor-signal output from an analog ASIC chip (e.g. several Kilohertz) using Cortex-M?

    This question was raised in the ‘Want to maximise your product design? See how a custom ASIC can help?' webinar, view all the questions in the round-up blog post.

  • Can SoC Verification be automated using Machine Learning? If so, how can we ensure 100% functional coverage?

    This question was raised in the ‘Want to maximise your product design? See how a custom ASIC can help?' webinar, view all the questions in the round-up blog post.

  • How is the SoC-based design validated? Is it done against some specifications or compliance?

    This question was raised in the ‘Want to maximise your product design? See how a custom ASIC can help?' webinar, view all the questions in the round-up blog post.

  • Assuming knowledge of standard off-the-shelf SoC and FPGA designs, what big challenges exists for an integrated solution?

    This question was raised in the ‘Want to maximise your product design? See how a custom ASIC can help?' webinar, view all the questions in the round-up blog post.

  • Is the DesignStart Eval compatible with heterogeneous multi-core design, e.g. Cortex-M0 with Cortex-M3?

    This question was raised in the webinar "Enhance your product with industry-leading processors - for no upfront license fee.”

  • Could you recommend a specific FPGA board for ARM Cortex-M0 and Cortex-M3 implementation?

    This question was raised in the webinar "Enhance your product with industry-leading processors - for no upfront license fee.”

  • Are DesignStart Pro royalties based on the number of cores instantiated in single chip? If so, what about permanent lockstep configurations?

    This question was raised in the webinar "Enhance your product with industry-leading processors - for no upfront license fee.”

  • If I am an individual how can I apply for the DesignStart program and get a prototype?

    This question was raised in the webinar "Enhance your product with industry-leading processors - for no upfront license fee.”

  • Fab costs prohibit many start-ups and small companies to pursue custom SoC development. Does ARM have any plans to help companies on this, maybe with some fab partners similar to the design partners

    This question was raised in the webinar "Enhance your product with industry-leading processors - for no upfront license fee.”

  • Can the DesignStart Eval RTL project provided be modified? For example, to add new ports or remove unused ones for customization.

    This question was raised in the webinar "Enhance your product with industry-leading processors - for no upfront license fee.”

  • Is there any documentation for design implementation on ARM Keil software?

    This question was raised in the webinar "Enhance your product with industry-leading processors - for no upfront license fee.”