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  • [Cortex-M33 FVP]:SecureFault with SAU disable

    Hello,

    I am using Cortex-M33 FVP model to run the Keil RTX TrustZoneV8M RTOS example.
    Have also tried to experiment with the memory map configuration and the corresponding SAU region programming for NS/S patitioning and the behaviour is as expected.

    However…

  • Cortex-M0 example system

    Hi,

    II refer to the example MCU system level in the document "arm_cortex_m0_designstart_eval_user_guide", put it into MPS2+ after synthesis, the software uses the following example in this directory.

    D:\CMPS3\AT510-MN-80001-r2p0-00rel0\systems…

  • Xilinx FPGA Block ROM is used as FLASH and how to load the program in to this?

    Hi,

    I am using the SoC design from Desgn Start - Eval version for Cortex-M0 with only modification of using Xilinx Block ROM as the Memory for FLASH ROM as well as for RAM.

    And my goal is to load the application into the FLASH ROM (Xilinx Block ROM) using…