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  • ARM Cortex ICode, DCode, System buses

    Note: This was originally posted on 26th February 2009 at http://forums.arm.com

    I'm a bit confused about the bus structure and memory model of ARM Cortex M3. First of all, does Cortex M3 actually have 3 physically separate buses coming out of it?
    …

  • Shortest code for memory to memory transfer

    Note: This was originally posted on 16th March 2009 at http://forums.arm.com

    Hi All,
        Can anyone tell me what is the shortest code I can use for cortex M3 to transfer (a few words) from one memory location to other(without using the DMA).  It should…

  • Cortex-M3 Hard Fault - find cause?!?!?!?

    Hello all,

    I'm new to the ARM platform and I'm having a problem discovering why my code is generating a Hard Fault.

    My hardware is an mbed platform board with the NXP LPC1768 processor.

    The code in question works when compiled using the mbed…

  • [Cortex-M33 FVP]:SecureFault with SAU disable

    Hello,

    I am using Cortex-M33 FVP model to run the Keil RTX TrustZoneV8M RTOS example.
    Have also tried to experiment with the memory map configuration and the corresponding SAU region programming for NS/S patitioning and the behaviour is as expected.

    However…