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  • Optimized RGB to YCbCr conversion on Cortex-M7

    Hi,

    Does ARM make available optimized routines for RGB/YCbCr conversions (e.g. RGB16/RGB888 to YCbCr 4:2:0 and 4:2:2) on Cortex-M7 (e.g. using SIMD instructions and intrinsics)?

    (and in general, is there such an optimized library for DSP and image processing…

  • Cortex-M7 minimum schematic ?

    I'm looking to start a new design based on the ARM Cortex-M7 and have been reading thousands of pages of documentation ( not done yet of course ). I am able to design my own schematics and PCBs so I'm trying to first determine the very bare minimum to…

  • Help Choosing a processor

    I have been given the task of selecting a suitable processor for a project in which we will have a dedicated processor.

    The project will involve configuring HW and inverting matrices in C.  We will use the Cholesky algorithm in double precision.  We don…

  • When will be the Release of "The Definitive Guide to Cortex M7" ??

    Hi Sir,

    may be the title of this question looks fun, but i am eagerly waiting for your next book "The Definitive Guide to Cortex M7" are you working on this book?? When could i Expect this book

    Thanks and Regards,

    Harshan.

  • mismatch between ARMv7-M ref manual and core_cm7.h

    The ARMv7-M reference manual notes there eight ITM trace enable registers called ITM_TER0 to ITM_TER7.  However, core_cm7.h only has one ITM_TER register.  Can you clarify?  Is it an error in core_cm7.h?

  • Using GPIO for timing execution of functions

    I have a need to measure the execution time of certain functions using an oscilloscope. When I enter the function I toggle a pin high, and before exiting the function I toggle the pin low.

    I'm using an STM32F7 (Cortex M7) processor and using armcc in…

  • Trying to find basic performance measurements of ARM cores

    Howdy, I was trying to find some basic performance benchmarks for a couple of different ARM cores: The Arm 926EJ-S, Cortex A9, and the Cortex M7.

    I am looking for primarily DMIPS (per MHz or a form that requires me scaling to my specific chip is fine…

  • Semihosting in DS-5

    Hi, I am trying to do file in DS-5 (evaluation version) using semihost, gettting errors (fopen returns -1). Is the eval version not able to do file IO?

  • Cortex-M7 VFMA usage

    Dear All,

    this is my first post and I hope I do not make any serious mistakes.

    My question is regarding the use case of the cortex-m7 VFMA/VMLA instruction.

    I am evaluating a polinomial for which the C compiler emits VFMA.F32 instructions. Out of curiosity…

  • Why Cortex-M7 doesn't support bit-banding?

    Cortex-M7 processors tends to be for the high performance applications. So why it doesn't support bit-banding if this has a lot of advantages to the code size and performance?

  • DMB, DSB, ISB on Cortex M3,M4,M7 Single Core parts

    I have been reading through the ARM documentation on memory and instruction barriers. 

    I have read that the single core ARMv7-M parts do not reorder instructions, as such the DSB and ISB are not needed, is this correct? 

    I have also read the same about…

  • Is a DMB required between loading BASEPRI and storing BASEPRI_MAX?

    Hi,

    I have a question regarding BASEPRI, BASEPRI_MAX, and DMBs as they relate to both the V7-M and V7E-M architectures.

    Let's say I have the following assembly,

    // stuff
mrs r0, BASEPRI
msr BASEPRI_MAX, #3
// more stuff

    Is it necessary to put a…

  • Looking for typical max frequency for Cortex-M CPUs

    I'm looking for information on the typical max frequency (or typical frequency range) for the Cortex-M cores, in 40nm. Is there any documentation on that? Thanks.

  • Raising priority of PendSV within NVIC when PendSV pending

    Hi,

    I'm trying to understand the behavior of raising (lowering numerical priority) the priority of PendSV in the NVIC of a Cortex M4 or M7 when PendSV is already pending. Below are the cases I'm grappling with,

    1) High priority interrupt ISR is…

  • Number of Integer and Floating point execution units in M7

    Hi guys,

    I have 2 doubts.

    1) the number of integer and floating point execution units in cortex M7

    2) is the number of pipeline stages different for integer and FP 

  • When an exception is taken into account

    Hi

    Related to ARMv7-M architecture:

    I am searching through all infocenter documents but still cannot find anything and answer this question: "When an exception is taken into account?" I mean, are exceptions only serviced after the current instruction…

  • MIPS of Arm cortex m7

    Hi.

    I need the MIPS of cortex m7 processor. The results which I saw on wikipedia were in DMIPS. But i need it in MIPS only.

    Can someone help me with it?

    Thanks,

    Shreyas

  • LDREX/STREX on the M3,M4,M7

    Doing some research of the LDREX and STREX it appears that the exclusivity address range for these instructions on the M3,M4,M7 is the entire memory space. Hence you can only use the LDREX/STREX with one address.   Does this not limit you to one Mutex …

  • Cortex M7 DSP moving average UMAAL

    Hello,

    I am looking to do a moving average function using DSP instructions of ARM Cortex M7. Unfortunately I couldn't find a direct example. My goal is to have variables for

    - the sum

    - the new value

    - the oldest value

    Then the algorithm is sum =…

  • how dose the PC run to startup.s when the mcu reset

    Hi，dear enginner：

        i want to know how the PC run to startup.s when mcu reset？

       The Definitive Guide to the ARM Cortex-M3 says address 0x00000000 is MSP‘，address 0x00000004 is ResetVector.

       But when I look at STM32F767, I find that 0x00000000 and…

  • After Embedded World: What’s Next for Embedded ML?

    There’s no denying that Embedded World (EW) is a whirlwind – 1000 exhibits, 35,000 visitors and over 2,000 industry participants – but now that it’s all over and the dust has settled, I wanted to take a moment to reflect on its impact, and consider the…

  • Does DS-5 support Arm Cortex-M Core FVP (for M7)

    Trying to look for an IDE that support FVP for the Cortex M7.  Does DS-5 support it? If not, what are my options?

  • arm_sqrt_f32() is missing in CMSIS CM7 math library

    It appears the CMSIS math library for Cortex-M7 is missing arm_sqrt_f32().  I ran objdump on the library and arm_sqrt_f32() is missing.  The library contains arm_sqrt_q15(), arm_sqrt_q31() but does not have arm_sqrt_f32().

    CMSIS_5/CMSIS/Lib/GCC/libarm_cortexM7lfdp_math…

  • Cortex M7 D cache activated without MPU been enabled

    Hi,

    I have question related to cortex M7 cache behavior.

    I noticed that whenever the MPU is disabled after power on reset then I activate data cache I get a hardfault (data cache is already invalidated before enabling data cache).

    This doesn't make sense…

  • Where can i find resources about creating program on cortex-m7 from scratch?

    I want to make full process with my hands: writing startup, linker script, init file, makefile configurate toolset and so far and so forth.