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  • "Dormant Mode" for Cortex M3/M4

    Hi,

    We are interested in minimizing startup time from deep sleep mode.

    Some of the older ARM cores implement a dormant mode whereby the CPU core context (state) is written to RAM prior powering it down, and then then restored after the CPU core  is powered…

  • about tail chaning of Cortex-M0

    Hello.

    I'm studying about the tail chaining of Cortex-M0.

    Is it same as Cortex-M3 or M4?

    Best regards.

  • cmsis NVIC question.

    Hello, Everybody. I have several questions.

    1. Please See the NVIC_Type structure. I don't understand about why ISER,ICER,ISPR and ICPR use size of array 1( I think It can use just __IO uint32_t ISER; ), and what does RESERVEDs do???

    2. I would like…

  • Race condition between wake up event and WFI on Cortex-M3/M4

    When I read below thread in arm forum, I still not clear which one is the safety way.

    Cortex-M4: guaranteed wakeup from WFI?

    There're two solutions mentioned above, using WFE instead of WFI, and swap __WFI() and __enable_irq().

    I can understand WFE…

  • Can we Modify the Flash Memory Access Permission with MPU( Memory Protection Unit)

    Hi Sir,

             Can i change Flash Memory Permission through MPU??

    Thanks and Regards,
    Harshan.

  • How long bitfields on which ARM?

    I need to be able to handle long bitfields as effectively as possible. Right now I need up to 64 bits in length.

    Are there instructions to set, clear and test individual bits in one cycle available for some of the architectures? Which? Particularly, will…

  • Help me jump into ARM world !(I know nothing but AVR)

    Hi,  Sorry if this is a long thread but i'm really confused.

    I program for AVR MCUs and also know about Arduino, I can program for different ATMEL MCUs with looking at datasheets, And i also programmed a few basic stuff on Cortex-M3 LPC1768, without…

  • Break Points and Watch Points

    Greetings,

                   Sir,i am working on SWD, after  Research on Break Point & Watch Point i found One Thing That There are Some Comparators will Do These Things but I am not Very Sure That How These are Work …

  • Get current active interrupt priority

    Hi everybody,

    We are working on a simple priority RTC (run to completion) framework for the Cortex M3/M4. Thanks to the NVIC/BASEPRI, we got most of this functionality for free but we want to extend it to user tasks.

    In our implementation we need to determine…

  • Recommended book on ARM

    HI,

    i'm an ICT professional (so also with an IT background) and very much interested in embedded development (IoT solutions). Until now I mainly did embedded development (mainly ARM m3, m4 microprocessors based development boards: eg Spark Core, TI CC3200…

  • will cortex m3/m4 enter a lockup mode if a serious fault happened while FAULTMASK is set

    Greetings,,

    what happens if FAULTMASK is set in cortex-m3/m4 and one or more serious fault happened like bus fault, MPU violation, invalid instruction, stack corruption.. etc will the processor enter a lockup? if not what would be the status of the processor…

  • Cheap alternative of J-Link Segger

    I am looking for some alternative of J-Link Segger for Cortex-M3/4 , the cheapest one is J-Link Base as J-Link Lite can be used only with evaluation boards, 

    Any suggestion ?

    I am using GNU arm gcc as toolchain and debugger and Eclipse as IDE, I…

  • TRACEDATA Capture issues

    Hi there,

    I am the author of the open source Orbuculum tools for SWO data parsing on CORTEX-M targets. I am currently expanding those tools by implementing 1, 2 & 4-bit parallel TRACEDATA capture from CORTEX-M3/M4 CPUs using a small FPGA connected to…

  • Where to find the execution cycles of Cortex m7 instruction

    for Cortex-M0, M3 and M4, I can find the execution time in their Technical Reference Manual > Programmers Model > Instruction set summary 里面查看

    http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0432c/CHDCICDF.html

    but for M7 It said that…

  • When will be the Release of "The Definitive Guide to Cortex M7" ??

    Hi Sir,

    may be the title of this question looks fun, but i am eagerly waiting for your next book "The Definitive Guide to Cortex M7" are you working on this book?? When could i Expect this book

    Thanks and Regards,

    Harshan.

  • How cortex-M4 handles data hazard situations in the pipeline?

    Hello to all,

    Since I am working on ARM Cortex-M4, I would like to know about the handling of the hazard situations (especially the RAW, WAR and WAW hazard situations) in the pipeline.

    Is the processor also use the method of "Forwarding" in order to handle…

  • MPU is not triggering MemFault or HardFault

    MPU is not triggering MemManage fault. I want to protect a memory region of 64 bytes starting from 0x20000000. I've configured the MPU registers accordingly, but when I write in a protected memory location, MPU does not trigger fault.

    Here's a code…

  • Forced Hardfault (INVPC) Exception Error

    Using ARM coretx-M chip set

    Getting random  INVPC hard fault exception error, while running iperf tool for measuring n/w throughput.

    Hard fault reg: 0x40000000

    xPSR: 0x01000000

    PRIMASK: 0x00000001

    CONTROL: 0x00000000

    Please help to find the possible root…

  • Does Cortex-M3/M4 continue with burst in response to ERROR?

    AMBA spec states that 'Master can choose whether to terminate current burst or continue with burst in response to ERROR'.
    What does Cortex-M3/M4 do in response to ERROR? Does it continue with burst in response to ERROR in some special cases?

  • DMB, DSB, ISB on Cortex M3,M4,M7 Single Core parts

    I have been reading through the ARM documentation on memory and instruction barriers. 

    I have read that the single core ARMv7-M parts do not reorder instructions, as such the DSB and ISB are not needed, is this correct? 

    I have also read the same about…

  • Interruptible Instructions on Cortex-M4

    The ARM Cortex-M4 Processor Technical Reference Manual states:

    To minimize interrupt latency, the processor abandons any divide instruction to take any pending interrupt. On return from the interrupt handler, the processor restarts the divide instruction…

  • When an exception is taken into account

    Hi

    Related to ARMv7-M architecture:

    I am searching through all infocenter documents but still cannot find anything and answer this question: "When an exception is taken into account?" I mean, are exceptions only serviced after the current instruction…

  • LDREX/STREX on the M3,M4,M7

    Doing some research of the LDREX and STREX it appears that the exclusivity address range for these instructions on the M3,M4,M7 is the entire memory space. Hence you can only use the LDREX/STREX with one address.   Does this not limit you to one Mutex …

  • V2M MPS2+: 'ERROR: FPGA did not configure.'

    Hi all,

    We have purchased an MPS2+ platform, and everything was going well, but since Friday we are facing an error we do not understand.

    When starting the FPGA configuration (by pressing the 'ON' button on the board), leds start blinking (the screen…

  • Hard Faults and MemManage Faults in Cortex m3/m4

    I wrote a simple program, where I am writing to an illegal memory location. Writing in an illegal Memory location generates a MemManage fault. And if MemManage is not enabled, HardFault in generated. But in my case hardfault is also not triggering.

    Here…