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  • What is the meaning of a 64 bit aligned stack pointer address?

    According to ARM Architecture Procedure Call Standard (AAPCS) on the ARMv6-M, and ARMv7-M architecture in  it says:

    "Although the processor hardware allows SP to be at any word aligned address at function boundaries, standard programming practice…

  • Hard Fault in cortex m4

    Hello All,

    Good Morning!

    I am working on Cortex m4.

    I have read following about hard fault ,

    "Bus Fault: detects memory access errors on instruction fetch, data read/write, interrupt vector fetch, and register stacking (save/restore) on interrupt (entry/exit…

  • Problems with interrupting LDM/STM Cortex M4?

    I am seeing stack corruption running a Cortex M4 that seems to be related to interrupting multicycle instructions.

    The interrupt occurs during a STMDB sp!, {r4, r5, r6, r7, r8, r9, sl, lr}

    The ICI bits at the time of the interrupt equal 7. This means that…

  • Current priority level of processor

    Hi,

    I have been reading about the exception mechanism of Cortex-M (M4 to be precise). The exception request is accepted by the processor if the current priority level of the processor is less than the incoming exception (this is one of the conditions to…

  • Indication to begin a program

    I need some indications to begin writing a program.

    Write a compare routine to compare 64-bits values , using only two instructions.

    Thanks for your indications !

  • Break Points and Watch Points

    Greetings,

                   Sir,i am working on SWD, after  Research on Break Point & Watch Point i found One Thing That There are Some Comparators will Do These Things but I am not Very Sure That How These are Work …

  • Endian in Cortex-M4

    Hello to all,

    I am working on ARM Cortex-M4. Since it has 32-bit address bus, therefore I assumed that each 32-bit instruction will be allocated a physical address location in the Flash. But while reading the disassembly of the code, I got to know that…

  • M4 Assembly - Set Enable also enables the Clear Enable Interrupt Register

    Hi,

    I have some assembly for Cortex M4 (Arm 7M Thumb), I want to enable an interrupt that is connected to a push button on an STM32 F407. It works, but for some reason when I enable the set enable register, the clear enable register also gets set ? Is…

  • DMB, DSB, ISB on Cortex M3,M4,M7 Single Core parts

    I have been reading through the ARM documentation on memory and instruction barriers. 

    I have read that the single core ARMv7-M parts do not reorder instructions, as such the DSB and ISB are not needed, is this correct? 

    I have also read the same about…

  • When an exception is taken into account

    Hi

    Related to ARMv7-M architecture:

    I am searching through all infocenter documents but still cannot find anything and answer this question: "When an exception is taken into account?" I mean, are exceptions only serviced after the current instruction…

  • DWT

    Hello,

    I use DWT in Cortex-M4 to catch instructions that write or read memory contents and the problem is it doesn't stop immediately where I expect, it stops after 2-3 instruction later than where it should and the contents of registers are overwritten…