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  • CM4: Can processor halt itself by writing DHCSR

    Hello,

    As part of my diagnostic regime I wanted the diag to halt when completed.  It doesn't seem like it can.  It seems to keep running when I 

      CoreDebug->DHCSR = (0xA05FUL << CoreDebug_DHCSR_DBGKEY_Pos) |
                         CoreDebug_DHCSR_C_HALT_Msk…

  • How cortex-M4 handles data hazard situations in the pipeline?

    Hello to all,

    Since I am working on ARM Cortex-M4, I would like to know about the handling of the hazard situations (especially the RAW, WAR and WAW hazard situations) in the pipeline.

    Is the processor also use the method of "Forwarding" in order to handle…

  • Does Cortex-M3/M4 continue with burst in response to ERROR?

    AMBA spec states that 'Master can choose whether to terminate current burst or continue with burst in response to ERROR'.
    What does Cortex-M3/M4 do in response to ERROR? Does it continue with burst in response to ERROR in some special cases?

  • What happens to upper half of 32-bit data bus when reading 16-bit chip?

    Hi guys, I am interested in exploring a scenario when Cortex M4 cpu performs a 16-bit static memory read when 32-bit memory is actually on the board.

    The 16-bit memory chip is connected to lower half of the data bus, signals D0..D15 and there are two…

  • What is the top level difference in features between Cortex-M33 and Cortex-M4?

    This is a very common question.

    The diagram below is a pictorial description of the differences followed by some explanations.

    Cortex-M33 v Cortex-M4 features

    Starting from the bottom:

    • Cortex-M33 is an implementation of the ARMv8-M architecture. Full details are in my blog on the 5…