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  • [Cortex-M33 FVP]:SecureFault with SAU disable

    Hello,

    I am using Cortex-M33 FVP model to run the Keil RTX TrustZoneV8M RTOS example.
    Have also tried to experiment with the memory map configuration and the corresponding SAU region programming for NS/S patitioning and the behaviour is as expected.

    However…

  • CMSDK - design multi-master bus

     asked: "with the M3 designstart CMSDK, is it possible to design multi-master bus? In the IoT Cortex-M TRM, only an ahb-lite structure is illustrated. That document does mention AHB and APB expansion through INTEXP[1:0] but what if there are more…