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  • What is the top level difference in features between Cortex-M33 and Cortex-M4?

    This is a very common question.

    The diagram below is a pictorial description of the differences followed by some explanations.

    Cortex-M33 v Cortex-M4 features

    Starting from the bottom:

    • Cortex-M33 is an implementation of the ARMv8-M architecture. Full details are in my blog on the 5…

  • What is the top level difference in features between Cortex-M23 and Cortex-M0+?

    This is a very common question too.

    The diagram is a pictorial description of the differences followed by some explanations.

     

     

    Starting from the bottom:

     

    -Cortex-M23 is an implementation of the ARMv8-M architecture. Full details here.

    -Using the same debug…

  • [Cortex-M33 FVP]:SecureFault with SAU disable

    Hello,

    I am using Cortex-M33 FVP model to run the Keil RTX TrustZoneV8M RTOS example.
    Have also tried to experiment with the memory map configuration and the corresponding SAU region programming for NS/S patitioning and the behaviour is as expected.

    However…

  • Is it possible to interface a high frequency sensor-signal output from an analog ASIC chip (e.g. several Kilohertz) using Cortex-M?

    This question was raised in the ‘Want to maximise your product design? See how a custom ASIC can help?' webinar, view all the questions in the round-up blog post.

  • How do I get the waveform dump file in simulate?

    Hi.

    I'd like to get the simulation waveform dump file when I do run the simulation of AT421-MN-80001.

    there is some options in makefile such as 

    # NC verilog option
    NCSIM_OPTIONS = -unbuffered -status -LICQUEUE -f ncsim.args -cdslib cds.lib -hdlvar…

  • CM3 DesignStart Build warning messages with Quartus Prime 17.0.2

    Hi,

    I am using Quartus Prime Lite 17.0.2 for building Cortex-M3 DesignStart RTL.

    I can successfully build the RTL, but I got some critical warnings as follows. Can I ignore these warnings? Is there any effects on the design by these warnings?

    Critical…

  • DesignStart Eval on Terasic DE10-Standard Board

    Hello,

    For my bachelor thesis I have to implement the RTL-Code of the Cortex-M3 in the DE-10 Standard Board.
    The FPGA on the Terasic DE-10 Standard is the Cyclone V  5CSXFC6D6F31C6.

    If I try to compile the ".sof" file of the Eval package in Quartus Prime…

  • About V2M-MPS2+

    Hi,guys.

    We have already  applied for Cortex-M3 DesignStart Pro and purchased the V2M-MPS2+ motherboards.

    To my knowledge, V2M-MPS2+ motherboards was designed for DesighStart Eval and can be integrated with arm Embed OS easily.

    So, my question is:

    1, can…