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  • What is TrustZone for ARMv8-M?

    As a product manager for the Cortex-M33, I see this question pop up a lot. Below is my version of the answer.

    Characteristics of TrustZone technology

    • TrustZone is the security foundation for billions of ARM Cortex-A processor-based systems
    • TrustZone…
  • A couple of use cases for TrustZone for ARMv8-M

    Root of Trust implementation – Connected devices with authentication requirements need a root of trust in the system architecture. This is particularly important for devices that can be updated over the air. In a system with TrustZone technology, code…

  • What is the top level difference in features between Cortex-M33 and Cortex-M4?

    This is a very common question.

    The diagram below is a pictorial description of the differences followed by some explanations.

    Cortex-M33 v Cortex-M4 features

    Starting from the bottom:

    • Cortex-M33 is an implementation of the ARMv8-M architecture. Full details are in my blog on the 5…
  • What is the top level difference in features between Cortex-M23 and Cortex-M0+?

    This is a very common question too.

    The diagram is a pictorial description of the differences followed by some explanations.

     

     

    Starting from the bottom:

     

    -Cortex-M23 is an implementation of the ARMv8-M architecture. Full details here.

    -Using the same debug…

  • [Cortex-M33 FVP]:SecureFault with SAU disable

    Hello,

    I am using Cortex-M33 FVP model to run the Keil RTX TrustZoneV8M RTOS example.
    Have also tried to experiment with the memory map configuration and the corresponding SAU region programming for NS/S patitioning and the behaviour is as expected.

    However…

  • TrustZone of the Cortex-M vs. TrustZone of the Cortex-A

    What is the difference between the TrustZone of Cortex M23/33 and the TrustZone of Cortex A?
    Can you provide documentation on this topic? May I start to prototype my Cortex M23 application on a Cortex A processor and then migrate to Cortex M23 when chips…

  • RTOS Design Considerations Version 2.0 - SVCall behavior question

    Hi,

    In RTOS Design Considerations Version 2.0 document, Section 2.2 ("SVCall and PendSV exceptions") following is mentioned.

    When the processor is in Secure state, the SVC exception handling sequence fetches the exception vector from the Secure…