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  • Cortex-M3 Hard Fault - find cause?!?!?!?

    Hello all,

    I'm new to the ARM platform and I'm having a problem discovering why my code is generating a Hard Fault.

    My hardware is an mbed platform board with the NXP LPC1768 processor.

    The code in question works when compiled using the mbed…

  • What is TrustZone for ARMv8-M?

    As a product manager for the Cortex-M33, I see this question pop up a lot. Below is my version of the answer.

    Characteristics of TrustZone technology

    • TrustZone is the security foundation for billions of ARM Cortex-A processor-based systems
    • TrustZone…

  • What is the top level difference in features between Cortex-M33 and Cortex-M4?

    This is a very common question.

    The diagram below is a pictorial description of the differences followed by some explanations.

    Cortex-M33 v Cortex-M4 features

    Starting from the bottom:

    • Cortex-M33 is an implementation of the ARMv8-M architecture. Full details are in my blog on the 5…

  • What is the top level difference in features between Cortex-M23 and Cortex-M0+?

    This is a very common question too.

    The diagram is a pictorial description of the differences followed by some explanations.

     

     

    Starting from the bottom:

     

    -Cortex-M23 is an implementation of the ARMv8-M architecture. Full details here.

    -Using the same debug…

  • [Cortex-M33 FVP]:SecureFault with SAU disable

    Hello,

    I am using Cortex-M33 FVP model to run the Keil RTX TrustZoneV8M RTOS example.
    Have also tried to experiment with the memory map configuration and the corresponding SAU region programming for NS/S patitioning and the behaviour is as expected.

    However…

  • Is it possible to interface a high frequency sensor-signal output from an analog ASIC chip (e.g. several Kilohertz) using Cortex-M?

    This question was raised in the ‘Want to maximise your product design? See how a custom ASIC can help?' webinar, view all the questions in the round-up blog post.

  • Can SoC Verification be automated using Machine Learning? If so, how can we ensure 100% functional coverage?

    This question was raised in the ‘Want to maximise your product design? See how a custom ASIC can help?' webinar, view all the questions in the round-up blog post.

  • Are DesignStart Pro royalties based on the number of cores instantiated in single chip? If so, what about permanent lockstep configurations?

    This question was raised in the webinar "Enhance your product with industry-leading processors - for no upfront license fee.”

  • What ASIL level can be achieved with the Cortex-M3 processor?

    This question was raised in the webinar "Enhance your product with industry-leading processors - for no upfront license fee.”

  • How do I start with simple example for study about boot rom and boot sequence?

    Hi.

    How do I start with simple example for study about boot rom and boot sequence?

    I'd like to make a simple architecture, but first of all, I have to make a L1 boot and L2 Boot code as I know.

    CM3 is connected with boot ROM and Flash.

    So Would you…

  • Has anyone had problems with implementing App Note AN387 using Cortex M0 r2p0 on a Cortex-M + dev board?

    All,

    I received the Versatile Express Cortex-M Prototyping System + and am using DesignStart. I powered on the board and the operating system booted up without any problems.

    In the V2M_MPS2/MB/HBI0263C/board.txt file, the following are the sequence of…

  • Cortex M3 on Arty A35T with Vivado 2018.3 Windows 10

    Hi. First of all, thanks for your attention in advance. I have to say that I am completely new in FPGA programming, but I could have never imagined that running an example with a documentation explaining it step by step could be so cumbersome and error…