Hello, Everybody. I have several questions.
1. Please See the NVIC_Type structure. I don't understand about why ISER,ICER,ISPR and ICPR use size of array 1( I think It can use just __IO uint32_t ISER; ), and what does RESERVEDs do???
2. I would like…
CORE: STM32F103ZET6
Hi,Pros.
Here Monkey comes agian
I have met a problem with my code,see below:
/* --------- code here --------- */ .section .data _sp_usart: .word _stack_usart _stack_usart: .space 0x100…
Hi everybody,
We are working on a simple priority RTC (run to completion) framework for the Cortex M3/M4. Thanks to the NVIC/BASEPRI, we got most of this functionality for free but we want to extend it to user tasks.
In our implementation we need to determine…
Hello!
I finally decided to share some info about a project I've been doing for the past 8 months. Currently it can be considered "alpha" or maybe "early beta" stage, but - despite literal meaning of these terms - the things that are already done (and…
I have a very simple CortexM3 based virtual platform example as below
The amba_pv_m2 is connected to a memory in the top. The BusDecoder master port address range is 0x0-0x3FFFFFFF
I have the following C program
#include <stdio.h>
int main(int…
Background I'm working part-time on a Cortex M0+ based SoC converting a very processor-intensive section of C++ code (inner-loop executed 10s of 1000s of times a second & compiles to over 400 instructions using GNU O3) and after almost 3 months of work…
