According to ARM Architecture Procedure Call Standard (AAPCS) on the ARMv6-M, and ARMv7-M architecture in it says:
"Although the processor hardware allows SP to be at any word aligned address at function boundaries, standard programming practice…
There's many references to Debugging a Hard Fault on Cortex-M3 & M4; eg
niallcooling's Developing a Generic Hard Fault handler for Armv7-M
also:
http://supp.iar.com/Support/?Note=23721
https://community.freescale.com/thread/306244 - which…
This article is a follow-on to Navigating the Cortex Maze. As a high-level overview, the earlier article provides an easy way-in to the ARM processor range. It covers Cortex-A (architecture ARMv7-A), Cortex-R (ARMv7-R) and Cortex-M (ARMv7-M).
But the…