Guten tag,
I am currently been keen focus on interfacing RTOS in ARM cortex Mx series. With ARM nomenclature, the Cortex-Mx series is designed for Hard-Realtime applications. Properties like low interrupt latency, few pipelines, no cache, no MMU make it…
Turn back the clocks three months and the events industry was in turmoil. Leading industry events across the globe were being canceled or scaled-down significantly, and the next opportunity of a face-to-face event was very uncertain. But now, our industry…
I want to make C_DEBUGEN (register DHCSR) zero.
I tried this. (CoreDebug->DHCSR = (unsigned int)0xA05F0000;)
But again, C_Debugen is set to 1.
I want to know how to set it to 0.
It is possible to force change using T32, but is it possible in code?
Hello i am a student at cphbusiness in Denmark, and i am currently doing a research project on the Cortex-m 4. i am hoping someone can help me understand what exactly is going on inside the processor. I have attached a picture, and i am hoping someone…
The Arm Cortex-M55 processor is the first processor with Armv8.1-M architecture which includes the implementation of Arm Helium Technology, also known as M-profile Vector Extension (MVE). Helium technology enables increased levels of Machine Learning and…
Hi,
In the Early Development Blog for the Cortex-M55 (https://community.arm.com/developer/tools-software/tools/b/tools-software-ides-blog/posts/start-early-development-on-arm-cortex-m55-processor), the mention that a run script to execute the FVP is provided…
The United Nations Development Programme (UNDP) – in conjunction with Hackster.io and supported by Arm – recently threw down the gauntlet to developers worldwide, challenging them to find globally sourced, locally implementable solutions to support developing…
Hi All!
I am working on STM32H745 dual-core controller and IAR Embedded Workbench for ARM toolchain V8.40.1 for development.
I have completed all my work on individual core test and debugging with help of ST-Link V3 as debugger but unfortunately, I am…
In a previous blog, I wrote about the reproducibility crisis in research, how it is impacting the quality of research and public trust in it, and how the community of knowledge can address this crisis. In this blog, I will focus on measures of performance…
Below are some useful links related to the Beetle IoT evaluation board
Hi all,
I am having a bootloader code wherein I will sending/receiving data via USART . I have configured USART to operate in interrupt mode.
USART functionality works perfectly fine independently. Verified this with multiple read/write instances.
When…
March 2020 was the month when all Arm training suddenly had to go virtual. With the outbreak of Covid-19, global lock downs and remote working for all those that could, classroom training from Arm had to adapt and had to do it quickly.
We'd already been…
Hello guys,
I am using an NRF chip with Cortex M4. Currently I am reading data from an accelerometer (12 signed bit ADC) and I have to get peak velocity. For that I am using the Omega arithmetic algorithm, as follows:
- remove offset from…
The reported cost related to cybercrime is estimated to be 6 trillion dollars by 20211. And that is just cybersecurity. As more devices are deployed, whether they are connected or not, they are under threat from many types of attacks, be it software,…
Is it possible to provide the caffe model (.protext and .caffemodel) for "CMSIS/NN/Examples/ARM/arm_nn_examples/gru/", similar to the one provided for cifar10 example under https://github.com/ARM-software/ML-examples/tree/master/cmsisnn…
I am trying to find the location of the register where the timestamp generator can be enabled on a Cortex-M4 processor.
In the CoreSight SoC Technical Reference Manual on page 3-210 it is mentioned that the register (CNTCR) is in the PSELCTRL region…
Spring has arrived for many, and with it comes the latest update of Arm Development Studio. This 2020.0 release adds the latest Arm IP support and useful new features across all the components. This release provides the first public support for the Cortex…
Arm recently announced the Cortex-M55 processor, the first to feature Arm Helium technology, also known as the M-Profile Vector Extensions (MVE), introduced with the Armv8.1-M architecture. The vector extensions enable increased DSP and machine learning (ML…
The advent of artificial intelligence (AI) is creating a wealth of opportunities ranging from better user experiences with consumer products to automated quality control on factory floors – and this list of AI-driven use-cases is growing exponentially…
Hi all.
I'm currently working on a Python-based framework for on-target firmware testing of firmware of Cortex-M MCU systems. The approach is heavily based on the use of the debug probe to perform unit as well as system tests.
The framework I have…
Hello,
Question about the "hint" instruction - WFI.
The armv7m arch manual (i'm using DDI0403_B, latest?) says it will come out of the suspended / low-power state if:
• A reset.• An asynchronous exception at a priority that, if PRIMASK…
We are making our DAC output a sinusoid of variable frequency depending on a button we press. The DAC does work when we hard code which button WE press but not with UART. With the UART handler (used for receiving the "button" we press and incrementing…
I'm working with the Cortex-M on digilent ARTY FPGA platform. I'm wondering how handling invalid address requests happen on a typical system. I'm guessing the address decoder in the AXI crossbar interconnect handles it somehow. Does it return an error…
Hi All,
I currently want to make use of the MPU. I have several functions which are required to be in privileged mode and are stored in a region set as privileged-read-only, user denied, executable.
This works fine when a BL or BLX instruction jumps here…
Cortex-M processors implement the CPUID register, through which it is possible to detect information about the core: part number (e.g. Cortex M7 or M4), revision and patch level (e.g. r1p2), etc.
Is there a register or a way to detect if the FPU has been…