Hello, everyone.
Let me post a question regarding booting Linux on ARM FVP (with Cortex-A9 MPCore).
I'm setting up an experiment which uses TrustZone on ARM FVP. I'm not sure which
kernel to run in the secure world, but am sure to run Linux in Normal…
Hi Experts,
I'm developing some kind of Secure OS on A57/53 big.LITTLE SoC.
While multi-core testing, I'm facing some wired problem on my world shared memory mechanism.
When I run world shared memory test on a single core (using affinity), it works…
Is there a reason why banked registers SP and LR can't be accessed as r13_<mode> or r14_<mode>, but
one has to use SP_<mode> or LR_<mode> instead? It makes macros and inline assembly difficult.
In document (ARMv7-A/R ARM Issue…
I was wondering about LDRT when the operand is rrx'd. Which where does the carry-bit come from?
LDRT{<c>}{<q>} <Rt>, [<Rn>], +/-<Rm> {, <shift>}
RRX Rotate right one bit, with extend. Bit[0] is written to shifter_carry_out…
Hi,
I have used some 32-bit microprocessor cores (non-ARM), which has a long word-length accumulator for some DSP operations, to avoid over-flow etc. After I check A8 core document, it is a surprise that I do not see any about this specification. It looks…
Hi everyone!!
I am looking to work on some projects using ARM. I have completed a basic course on ARM M3/M4 (UT Austin 6.01x by Jon Valvano and Ramesh Yerraballi) online. Now, I want to learn advanced things, especially real-time applications. How should…
I am using beaglebone which has the processor TI Sitara AM335X. I want to make use of Neon coprcessor for my project, To enable neon, I have to follow these commands. But I can't access these registers ( especially FPEXC…
Hello experts,
I would like to ask the reason why the exception frame forms on PSP in the Cortex-M architecture.My understanding is that MSP (Main Stack Pointer) is the interrupt stack pointer and PSP (Porcess Stack Pointer) is the normal (user) stack…
Hello,
I’m new to ARM architecture and was looking to get a better understanding of how it works. Most notably, the Cortex-A series and its DSP functionality.
When looking through the NEON SIMD page on ARM's webpage (NEON - ARM), it mentions that…
I am working on bootloader porting to ARM v8 platform. I am facing a problem in enabling MMU in execution level-1 EL1.
I am not able to set sctlr_el1.M bit when ever i try to set this bit the instruction won't complete. I think it…
Hi ARM experts,
For shareability attribute, have some confusions:
1 For a memory location with cacheability attribute, does hardware do "flush" action after "writing" to push data to end if shareability attribute is also set. Otherwise…
Hi arm experts,
I wrote some simple C functions to check if the result of memcpy is expected after enable MMU and data cache on Cortex-A53. The assembly (got by disassembling with aarch64-none-elf-objdump) of the one of these functions…
Hello experts,I feel I am an amateur.I tried to work the performance monitor of Cortex-A9 but it did not work.The followings are my codes.Please tell me what was wrong.
mov r3, #0 mcr 15, 0, r3, cr9, cr12, {0} // PMCR PMU disable…
I have a beaglebone black and running a very basic app using starterware. As soon as the app starts executing i copy the CPSR values in memory. The value of CPSR is super surprising
6000019f
which means it is in SYS mode and IRQ, ABORT disabled and FIQ…
Hi, we are using arm cortex-a9 booting from spansion s25fl256. We are confused why the spi driver forces to limits flash size to 0x1000000 (16M). It's normal when first bring up and into linux. However, we find the uboot is broken or overrided and can…
Hi, I make a software for Cortex-A9 and Cortex-M4 (both uni-processor system).
Question.
Is 64bit-aligned STRD(64bit memory access) atomic ?
(I know tha It is not atomic, but i don't know behavior.)
For example:
LDR R2,=buff
mov R0, #1
mov R1, #2
STRD R0…
I was going through the arm v8 mmu page table formation, when it's compared to arm v7 it is completely different.
I could…
I want to benchmark my program running on Linux on an Altera Cyclone V SoC board, but it turns out that the values returned from the ARM Cortex-A9 PMU cycle counter suggest that some sort of CPU frequency scaling is active, which is confusing me…
Is it possible for me to cross compile the hello Trust Zone example referenced here: Cortex-A9 TrustZone example ? The build file contains the command options for the arm compiler. I do not have the board this example was meant for, and I am trying to…
Is there any document on feature wise comparison chart on the Cortex A series of processors ?
Like,
Cache for Cortex A8/9/52...
MMU for cortex A8/9/52..
What's the difference between core, processor,cluster and CPU?
I am using Omap3515 (Arm Cortex A8). Enabled I-Cache, D-Cache, Branch Prediction and MMU.
I am getting a data abort, if I try to copy a frame buffer of 600KB from an external memory region to another external memory region. After the data abort, I could…
Hello everyone.
I am new usage of Allwinner A20.
I read in Cortex-A7 specification, that it have DSP & SIMD extensions.
And if there are digital processing unit in processor, can i use it? Can i drop on it some code, as any other DSP? And if yes, will…
When I read about Thumb2 instructions, I have such a question: How many states for a Coretx A8? I know it has ARM and Thumb states. Thumb2 instruction is belong to Thumb state? Then does A8 have a pure Thumb instruction besides Thumb2 set?
Thanks,
I heard that some 10-Gb Ethenet chip embedded an ARM core. I am curious about what type of ARM (A, M or R) is embedded in such a high speed Ethernet ASIC. I feel that it may be a R series ARM. Is it right? Due to such a high speed data rate, what chip…