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Hello 

I'm working on the Bootloader stage (EL2), I'm trying to enable Interrupts with gic v3 in that stage

I've enabled routing IRQ, FIQ and Aborts from EL0, EL1 and EL2 to EL2  using these piece of code 

MRS X0, HCR_EL2
AND X0, X0, 0xFFFFFF…

Hello,

I'm working with i.MX8DX (Dual Core CortexA35 + CortexM4) with the following simplified caching system:

My need is to flush a cached memory area to RAM in order to be viewed by the M4 core, unfortunately this area maybe cached by Core 0 and…

Hi,

I am using iMX 8X which has 1 cluster of 4 Cortex-A35 cores, with DDR3L (DDR3-1866) with ECC enabled.

I performed some measurement for MEMCPY and MEMSET functions to have an estimate of the DDR bandwidth, with one cortex-A35 core running. Here are…

I am working on project and i used A35 to measure the performance of Application and this application will be ported on M4 , is there a fixed ratio or an equation so i can estimate the execution time of the application on CM4 ?

Hello,

For a CortexA35, when reading the system counter clock frequency CNTFRQ_EL0, I found out that the frequency is 8 MHz.

Is this normal? For a target running in GHz?

The target is i.MX8QXP (Quad-Core CortexA35).

Counter-timer Physical Count register CNTPCT_EL0 always reads zero on FVP_Base_Cortex-A35x1. 

I expect the value of this register to change over time. 

I set $CNTFRQ_EL0=35000000, and $CNTP_CTL_EL0=5.

What is the possible reasons, and how is there any configuration…

Hello,

I'm developing a Baremetal application running on ARM Cortex A35 (ARMv8).

I have succeeded to enable the Caches and MMU in EL-1.

My questions are:

1. Can I enable the MMU and invalidate and enable the Caches in EL-2 without enabling them…

Hi,

ARMv8-A specification mentions revisions and options. I cannot find Cortex-A35 adheres to which exact version: ARMv8.1, 8.2, 8.3? I want to know which of the extensions described in the generic ARMv8-A spec are really available in that core.

Thanks…