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  • Which ARM processor is HSA compatible?

    Hi,

    I am new to the ARM community. I am currently studying the HSA (Heterogeneous System Architecture). ARM is member of this foundation.

    I wonder which processor from ARM is HSA enabled? And on which devkit (raspberry, ODROID, or other) So I can use it…

  • On Chip RAM is slow after enabling MMU, and using external ram aborts

    Hello All,

           I am using Omap3515 (Arm Cortex A8). Enabled I-Cache, D-Cache, Branch Prediction and MMU.

    Issue 1:

    But what I could notice is code region in external ram is executing faster than internal ram.

    If I disable…

  • Supported AXI transfers on Cortex-A9?

    Hi folks,

    The technical reference states that only a subset of possible AXI transactions are actually generated.

    This is described in http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0388f/Babiaggf.html

    What happens for this table if the master…

  • Can we run the Cortex-A53 cores at different clock speeds ?

    Dear ARM Group,

    Can we run the A53 cores at different clock speeds?

    if YES,  How does it effect the complete A53 (L2 cache etc) and system?

    if NO,  What are the constraints ?


    could you please give a detailed description on this?


    Thanks,

    Ravinder…

  • updating CPSR in USER UNPRIVILEGED mode

    as we know supervisor mode is priviliged and user is not. at reset time in debugging mode, i read the cpsr it is 0x1d3 means in supervisor mode, so i can change CPSR so i changed it to 0x1d0 which is user mode, since user mode is unpriviliged so i must…

  • How does128Byte WriteLineUnique transaction map to a cache with 64Byte cache line size?

    Hello,

    I have an IP with an ACE-Lite I/F which can issue a 128Byte write transaction with a "WriteLineUnique" type. I  the system there will be a cortex A7 master(64bytes cache line). My question is: in case of such transaction (WriteLineUnique with 128bytes…

  • how to set endianness in ARM Cortex-A8

    Hi,actually i need to run big endian code but i don't know how to set endian option in cp15 registers could any suggest me how to set EE bit set

  • share memory between core0 (linux) and core1 (bare-metal)

    Hello,

    i want to use the arm cortex a9 to share memory between both cores. are there any examples online?

    Thanks,

    Mike

  • Power Management Options in Cortex A

    Hi Experts,

    Whether the ARM provides the power management controller inbuilt in the cortex A5x processors or it provides signal pins suitable for easy integration with the power management controllers ?

  • Usage of Split/Lock Configuration

    Hi Experts,

    What is the use case of split/lock configuration in the Application processors ?

  • IRQ handler not called by ARM A53

    I'm testing GIC and ARM A53 connectivity. I can see that GIC is forwarding the IRQ request and ARM core has received it(shows in ISR reg). However, my IRQ handler is not getting called. Here is how I'm registering it..

    void main () {

    ...

    __enable_irq…

  • code compile using -mcpu for ARM platform

    When using gcc to compile c code for ARM platform, we set object platform by using:

         -mcpu = xxxxxx

    To what extent will that affect results of compiling ?

    For example:

         -mcpu = cortex-a8

    and

         -mcpu = cortex…

  • General Feature of Cortex processors on cache coherency

    Hi Experts,

    Is there any general feature available in the cortex processors to realize the cache lines by DMA through AXI ?

    I found some features like CCI module available to provide this feature in multi-core environment. Other than that, is it possible…

  • Re-entrant IRQ handler for A53

    Hello all,

    I have a A53 based platform. There are multiple IRQ sources, some of which fire at the same time. To avoid recursive IRQ handler calls, I have disabled IRQs' on entry in IRQ handler and enabled them befor exit. However, at one point, there is…

  • How SMMU will override the memory attribute of the master which have MMU/MPU embedded?

    For example, one M4 is a client of SMMU, and its MPU had been configured to map some memory(MEM_A) as inner outter write-back, how the configureation of SMMU context transcation table will affect the access attribute, say, the transcation table mark …

  • CPUID information about ARMv8 core

    Hi experts,

    I want to know if there are CPUIDs information in CHI interface about IP A53/57 Mpcore? and can CCN504 transfer the CPUIDs to Slave device? for example, AXI_USER?

    Thanks.

  • The merit of data cache cleaning

    Hello everyone, my 1st question to the ARM community; please excuse my ignorance.  Fairly recently, I shared OCM (on-chip-memory) on Xilinx Zynq processor (which is dual ARM Cortex A9).  To pass message between the 2 cores, I followed the Xilinx example…

  • system requirements

    what are the minimum hardware requirements to setup wifi on arm-7 processors.

  • How to run an ARM 32bit binary on Juno Board in Linux and Android ?

    hi, guys:

    Currently, i want to execute a Cotex-A9 binary compiled by ARMCC on Juno board(OS is linux).

    But when i ran it, it reported that "XX: No such file or directory".

    My questions are:

    (1) Did somebody meet this problem before ?

          and could…

  • Cortex-A72 and Cortex-A5x series boards

    Hi Experts,

    Is there any sample development boards available on Cortex-A72/5x series ?

    Regards,

    Techguyz

  • MRS/MSR (Banked register)

    What can be accessed by MRS/MSR in user mode?

    In ARMv7-A/R ARM there is an encoding for ARMv7VE (A1):

    B9.3.10      MSR (Banked register)
    cond  0 0 0 1 0 R 0 0        M1      …
  • Cortex-A9/GIC: de-activate an active interrupt

    Hi

    my situation: Running an OS in normal-world which due to an (user) error enters safe state with interrupts disabled. The Hypervisor enters by an FIQ (watchdog) and should reset the normal-world.

    No the problem: If the normal-world error happens in an…

  • Dhrystone Testing on Cortex A9: disabling Prints increases the DMIPS.

    i am seeing an issue while doing Dhrystone test. i am using Dhrstone source code of version 2.1.

    when i run this source code on LINUX platform, i got DMIPS/MHz =1.6

    but there are some printing commands that prints variables used, when i disable them i got…

  • ARM FULL VIRTUALISATION SOFTWARE

    Does anyone have details of the current situation in this area? For example, has ARM recently announced any related product(s)? What products are available for the Cortex -A17, for example?  In particular, what are the non-proprietary options, if any…

  • does different arm TRM revisions also have changes in Hardware?

    Hi

    I have an inquiry. our company is using Cortex-A9 quad Core. So in ARM website there are many technical reference manuals for the same in different revisions , such as:

    r2p0

    r2p2

    r3p0

    r4p0

    r4p1

    so what should i follow?

    or should i follow latest revision?

    or…