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  • Cortex A53 Bare metal booting have FIQ exception. How to debug?

    Hi

    I study coresight test with cortex A53 CPU.

    I get FIQ interrupt when I running helloworld test in ini_libc function. But I don't known why.

    I use gcc-linaro 4.9 toolchain : aarch64-none-elf-gcc  with glibc 2.14

    Set CPU config pin aa64naa32 to 1…

  • timestamp generator register location on Cortex-M4 (PSELCTRL CNTCR)

    I am trying to find the location of the register where the timestamp generator can be enabled on a Cortex-M4 processor.

    In the CoreSight SoC Technical Reference Manual on page 3-210 it is mentioned that the register (CNTCR) is in the PSELCTRL region…

  • Design considerations for implementing flash program download

    Hello,

    I'm workign in a SoC integration of a Cortex-M0 core. I've done my research but I can't seem to find an answer to an, in theory, easy question. Appreciate if someone can point me on the right direction.

    We have prototyped the Cortex…

  • Coresight Architecture: Is it possible to include AHB ROM tables as part of system ROM table?

    How to identify all the coresight ROM tables present in an SoC? Can APB-AP ROM table and AHB ROM tables co-exist as part of a single ROM table in the system memory?