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  • System wide cache flush

    Hello,

    I'm working with i.MX8DX (Dual Core CortexA35 + CortexM4) with the following simplified caching system:

    My need is to flush a cached memory area to RAM in order to be viewed by the M4 core, unfortunately this area maybe cached by Core 0 and…

  • Cache clean of translation tables stops execution?

    Hi,

    I am currently working on an integrity enforcer running in a modified version of the ARM trusted firmware in EL3. To gain access to the memory I added 4 1GiB entries to the translation tables located in the TTBR0_EL3.

    Now I am trying to hook the pagefault…

  • io coherency and shareability

    Hi,

    I have been reading about io coherency and the inner/outer shareability (SH bits in PTE). I kind of understand the concept of both but need help to connect the 2 concepts together. Lets assume a platform with (runs only one OS):

    - CCI-400
    - A53 Cluster…

  • What is difference between DCCIMVAC and DCIMVAC?

    The DCIMVAC represents a cache invalidate work. But one specific remark is that it will clean the data if the data is dirty before invalidation. Refer to followings

    /******************************************************/

    6.2.4 Data cache maintenance…

  • How to flush write buffer when memory attribute is normal_nc

    Hi,

    I am working on access pcie bar in armv8-a cpu(cortex-A5x) powered soc. Right now, I encounter an issue about (maybe) coherent issue.

    When I write data(4 bytes aligned) to pcie bar with ioremap_wc, there is some incorrect data. And it is correct…

  • Cache Coherence

    Hi ,

       I am working on ARM Multiprocessor. The Following is scenario for Cache coherency . Please let me know if it is valid.

       1. Bring Core 1 out of reset.

       2. Bring Core 2 out of reset.

       3. Invalidate Core 2 data cache…

  • MOESI state encoding of Cortex-A7

    Hi,

    I am looking at Cortex-A7 TRM, In "Direct Access to Internal Memory"

    we can see several information regarding a cache line. Those are:

    1. Current data in cache

    2. its 4-bit MOESI state,

    3. Outer Memory Attribute

    4. its tag

    5. NS State.

    However…

  • Cache cleaning and invalidating in ARM Cortex-A

    Cleaning or invalidating the L1 cache and L2 cache will not be a single atomic operation. A core might therefore perform cache maintenance on a particular address in both L1 and L2 caches only as two discrete steps. If another core were to access the…

  • Why A9 is multicore by A8 doesn't

    Hi Experts,

    Which factor in processor decides whether it can be used in multi-core or not ?

    Like as per my understanding A8 is used in single core whereas A9 is used in multi core. So which distinctive feature in A9 favors the multi core application ?

  • General Feature of Cortex processors on cache coherency

    Hi Experts,

    Is there any general feature available in the cortex processors to realize the cache lines by DMA through AXI ?

    I found some features like CCI module available to provide this feature in multi-core environment. Other than that, is it possible…

  • ACE-Lite

    Hi,

        Can anyone throw some light on ACE-Lite Slaves

         a ) Do they have inbuilt coherent caches? Can they be snooped?

         b) What type of ACE-Lite transactions are directed to them and what are the responses?…

  • VMSAv8-64 and spinlock

    Hi,

    I'm trying to implement a spin-lock to synchronize the execution of all cores Cortex-A53 on my Xilinx-ZCU102 board, but I have some issues maybe due to a wrong configuration of the VMSA and cache coherence.

    I'm writing bare-metal code, without…

  • shareability attribute for armv8 cortex a-53

    Hi,

    I have a system with a multiple quad core clusters with Cortex A-53 and the CCN-512. L1 through L2 are integrated caches where L3 is an outer cache in 8xHN-F of the CCN512.

    My question is how should I interpret the shareability domain: inner, outer…

  • How to invalidate cache (NVIDIA Drive PX2, ARMv8)

    Hey,

    on our development board we use PCIe to exchange data between the two Tegras on a NVIDIA Drive PX2.

    Basically the data coming across NT ports acts like a DMA engine writing to system RAM. With an interface function from the API of the PCIe-chip we…

  • ARM cortex R5 Performance is decreased by 20% after enabling Cache coherence

    Currently working on Xilinx Zynq US+ soc where R5(2 cores in lock step) and A53 (4 cores) , PL and GPU are mounted onto a single chip.

    so far we were using the concept of software based cache coherency mechanism to communicate between R5 and A53 worlds…

  • How to handle clean operation in Data Cache

    Hi,

    I have a question.

    when a processor sends a clean request to data cache, how data cache should behave?

    1. does it need to evict all cache lines present in cache (including clean lines) or does it evict only Dirty lines.

    2. if dirty lines to write…

  • ARMv7-A: Cache maintenance operation by VA, performance

    Hi,

    according to this talk, cache maintenance should always be performed by VA and not by set/way except during boot or shutdown. However, invalidating/cleaning a block of data by VA requires a loop to run over the entire memory block (in steps equal…

  • Extended System Coherency - Part 3 – Increasing Performance and Introducing CoreLink CCI-500

    Chinese Version 中文版： 扩展系统一致性 - 第 3 部分 - 性能提升和 CoreLink CCI-500 简介

    This week we announced the launch of a new suite of IP designed to enhance the premium mobile experience. A central part of this suite is the ARM CoreLink CCI-500 Cache Coherent Inter…

  • Extended System Coherency: Part 2 - Implementation, big.LITTLE, GPU Compute and Enterprise

    Chinese Version中文版：扩展系统一致性 - 第 2 部分 - 实施、big.LITTLE、GPU 计算和企业级应用

    This is the second part of a series of blogs about hardware coherency. In the first blog I introduced the fundamentals of cache coherency. This part talks about the implementation of hardware…

  • Exploring How Cache Coherency Accelerates Heterogeneous Compute

    Cache Coherency and Shared Virtual Memory

    The Heterogeneous System Architecture (HSA) Foundation is a not-for profit consortium for SoC IP vendors, OEMs, academia, SoC vendors, OSVs and ISVs whose goal is to make it easier for software developers to…

  • Extended System Coherency: Part 1 - Cache Coherency Fundamentals

    Chinese Version 中文版：扩展系统一致性 - 第 1 部分 - 缓存一致性基本信息

    Introduction

    The theme of TechCon 2013 was “Where intelligence connects” and in many ways hardware system coherency is an important part of connecting the intelligence of an SoC. This year I presented…

  • Why linux set memory as inner shareable in multi-cluster ARMv8 cores?

    Hi, 

    I have board with two clusters, one has 4*A57 cores, and the other has 4*A53 cores.

    The A57 cluster has its own L1 and L2 cache, A53 cluster also has its own L1 and L2 cache. Between the clusters there is a CCI.

    There is no L3 cache. So the memory…

  • Exploring the ARM CoreLink CCI-500 performance envelope - Part 1

    Introduction

    You may have noticed the ARM announcement last week of a group of Premium Mobile products (if not you can find it here ARM Sets New Standard for the Premium Mobile Experience - ARM) covering a new core processor IP, new GPU IP and a new…

  • Using Portable Stimulus in the Arm World: Creating bare-metal SW coherency scenarios

    In my last blog (Navigating SoC Verification with Perspec Portable Stimulus) I introduced the Accellera Portable Stimulus Standard (PSS) and how Cadence Perspec System Verifier supports the creation of portable baremetal Arm SoC integration tests using…

  • Is Cache Stashing introduced in DynamIQ similar to IO coherency?

     IO coherency also allows device to access coherent memory space. The only difference I noticed is that cache stashing connects device directly with cluster, however, IO coherency transactions need to go through system interconnect.