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  • Cache clean of translation tables stops execution?

    Hi,

    I am currently working on an integrity enforcer running in a modified version of the ARM trusted firmware in EL3. To gain access to the memory I added 4 1GiB entries to the translation tables located in the TTBR0_EL3.

    Now I am trying to hook the pagefault…

  • MOESI state encoding of Cortex-A7

    Hi,

    I am looking at Cortex-A7 TRM, In "Direct Access to Internal Memory"

    we can see several information regarding a cache line. Those are:

    1. Current data in cache

    2. its 4-bit MOESI state,

    3. Outer Memory Attribute

    4. its tag

    5. NS State.

    However…

  • VMSAv8-64 and spinlock

    Hi,

    I'm trying to implement a spin-lock to synchronize the execution of all cores Cortex-A53 on my Xilinx-ZCU102 board, but I have some issues maybe due to a wrong configuration of the VMSA and cache coherence.

    I'm writing bare-metal code, without…

  • shareability attribute for armv8 cortex a-53

    Hi,

    I have a system with a multiple quad core clusters with Cortex A-53 and the CCN-512. L1 through L2 are integrated caches where L3 is an outer cache in 8xHN-F of the CCN512.

    My question is how should I interpret the shareability domain: inner, outer…

  • Why linux set memory as inner shareable in multi-cluster ARMv8 cores?

    Hi, 

    I have board with two clusters, one has 4*A57 cores, and the other has 4*A53 cores.

    The A57 cluster has its own L1 and L2 cache, A53 cluster also has its own L1 and L2 cache. Between the clusters there is a CCI.

    There is no L3 cache. So the memory…

  • ARM cortex R5 Performance is decreased by 20% after enabling Cache coherence

    Currently working on Xilinx Zynq US+ soc where R5(2 cores in lock step) and A53 (4 cores) , PL and GPU are mounted onto a single chip.

    so far we were using the concept of software based cache coherency mechanism to communicate between R5 and A53 worlds…