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  • Cache clean of translation tables stops execution?

    Hi,

    I am currently working on an integrity enforcer running in a modified version of the ARM trusted firmware in EL3. To gain access to the memory I added 4 1GiB entries to the translation tables located in the TTBR0_EL3.

    Now I am trying to hook the pagefault…

  • shareability attribute for armv8 cortex a-53

    Hi,

    I have a system with a multiple quad core clusters with Cortex A-53 and the CCN-512. L1 through L2 are integrated caches where L3 is an outer cache in 8xHN-F of the CCN512.

    My question is how should I interpret the shareability domain: inner, outer…

  • ARMv7-A: Cache maintenance operation by VA, performance

    Hi,

    according to this talk, cache maintenance should always be performed by VA and not by set/way except during boot or shutdown. However, invalidating/cleaning a block of data by VA requires a loop to run over the entire memory block (in steps equal…

  • Introducing AMBA 5 CHI protocol enhancements: Specification now available

    In 2013 Arm announced the AMBA 5 CHI protocol to provide the performance and scale required for infrastructure applications such as networking and data center. The protocol has been highly successful and has been the foundation for Arm many core systems…

  • Exploring the ARM CoreLink CCI-500 performance envelope - Part 1

    Introduction

    You may have noticed the ARM announcement last week of a group of Premium Mobile products (if not you can find it here ARM Sets New Standard for the Premium Mobile Experience - ARM) covering a new core processor IP, new GPU IP and a new…

  • Cache maintenance and DMA

    Greetings ARM community,

    I have been tasked with cache maintenance.  The necessity popped up because of DMA issues on USB.

    As a quick (not perm solution) I used the invalidate all routine.  While obviously not nominal in anyway

    it does allow me…