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  • System wide cache flush

    Hello,

    I'm working with i.MX8DX (Dual Core CortexA35 + CortexM4) with the following simplified caching system:

    My need is to flush a cached memory area to RAM in order to be viewed by the M4 core, unfortunately this area maybe cached by Core 0 and…

  • Cortex-A35 cache partitioning

    Hi,

    I am using a Cortex-A35 (Armv8-A) in a processor and I am looking for any technique that could allow the L2 unified cache to support partitioning between running processes (for non interference between them, for safety reasons; as instance 256KB for…

  • COrtex M7 cache hit rate measurement

    Hello community,

    I have a Cortex M7 based product, and I want to measure the cache hit rate in different applications.compared to the cortex R5 the M7 does not embed a PMU.

     Do you have some idea on how to measure the cache hit rate in the ARM M7 core?

    …

  • Can I manually flush the GPU cache in OpenCL kernel code?

    Hi all,

    I am playing with Mali T624 and OpenCL. By playing the kernel-space midgard driver, I am now able to access some I/O memory in the OpenCL kernel. However, the I/O memory I am accessing is volatile. For example, assume we have a kernel function…