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  • aarch64 MMU: skipping first/second level tables

    Hi !

    on armv7 [1] / aarch32 [2] MMU, when using Long descriptor, when the virtual space described by ttbr0 is small enough (1Gb here), the level 1 translation can be skipped, leaving only two levels of translations.

    However I saw nothing of the like in…

  • Juno r1 Shareability Memory Attributes

    Hi experts,

     

    I'm using a Juno r1 board for some cache-related research experiment so I'm studying the related memory attributes such as cacheability and shareability.

     

    I found the manual mentioned that: " the division between inner and outer is…

  • Arm Architecture – Armv8.2-A evolution and delivery

    One thing is certain in this world – everything is changing, whether evolution or revolution and Arm Architecture is no exception. In this case the Arm v8 has evolved initially to v8.1-A and now to v8.2-A, both of which are now available in the

  • VTTBR_EL2 alignment

    Hi folks,

    in Armv8 reference manual, in the description of the VTTBR_EL2 register, the BADDR fields seems to have alignment constraints:

    Translation table base address, bits[47:x]. Bits [x-1:0] are RES 0.
    The AArch64 Virtual Memory System Architecture chapter…
  • Getting ERROR "unknown mnemonics for UQSUB8 instruction"

    Hi community,

    I have tried to compile the source code for openVG
    I have given proper cross compiler which is required by the platform still I am getting the error of unknown mnemonics for the instruction UQSUB8

    Environment:

    - Linux platform

    - CROSS COMPILE…

  • Is it possible to implement EL3 AArch64 and change it later to EL3 AArch32?

    I was reading the ARM architecture reference manual... and thought

    Is it possible to implement EL3 AArch64 and change it later to EL3 AArch32?

    How to change is...

    If I start on cold reset, it will start at EL3 AArch64.

    Right after the cold reset, I set the…

  • ARMv8-A 数据类型

    HI expert:

        最近一直在看ARMv8架构的spec,在网上下载了一个的编译器,请问在具体使用ARMv8时和之前在ARMv7上关于各种数据类型所占的字节数有区别吗?比如,int, long, long long, pointer等数据类型的大小.

    麻烦解答一下,谢谢!然后能够推荐一款编译器用于Cortex-A53开发?

  • [新闻]ARM推出全新超高能效Cortex-A32处理器, 扩大嵌入式与物联网产品阵容

    Cortex-A32_Block_Diagram.png

    2016224日,北京讯——ARM针对下一代嵌入式产品推出ARM® Cortex®-A32,为超高能效应用处理器系列再添新成员。Cortex-A32处理器采用ARMv8-A架构,赋予功耗有限的32位嵌入式应用更多优势。相较其他同类处理器,Cortex-A32拥有最小体积和最佳的能效表现。

    ARM 处理器部门总经理James McNiven表示:“ARM提供无与伦比的处理器产品组合,驱动数十亿计的超高能效嵌入式设备。Cortex-A32处…

  • 关于ARMv8中不同Security状态下异常向量表的问题

    Hi,各位专家:

        在ARMv7-A架构中,共有四张异常向量表,即Secure状态下的exception table, Non-Secure状态下的exception table,Monitor Mode下的exception table,以及hypervisor模式下的异常向量表,因为在不同Security状态下,VBAR寄存器是banked,所以它可将不同security状态的异常向量表分开,即Secure状态和Non-secure状态对应不同的exception table.…

  • Random behavior with SCTLR_EL1 reset values

    Hi,

    I am working on Juno and I am using SCTLR_EL1 reset value based on A53 spec is = 0x00C50838

    but If I look to ARMv8 spec it shows some reserved bits as 1 and considering that reset values = 0x30D50800.

    I am seeing some MMU random behavior at EL1 based…

  • I want to know how to invalidate or clean to cache only used secure-world

    Hello experts.

    I making a security operating system using trustzone using ARMv8 big-little core.

    I face some probleam of cache clean or invalidate.

    I want to cache flush to used only secure-world memory based on virtual memory, no flush non-secure world…

  • Issue with exception handler

    Hi,

    I am facing an issue where I am setting timer at Guest EL1 (NS) mode and trying to route this interrupt to EL2.

    I do see that when timer expires the interrupt is pending (using generic timer PPI 30) in GICD_ISPENDR (bit 30 set) but control reaches to…

  • CNTP_CVAL register write from EL1-NS ("Config-RW")

    Hi,

    I am trying to setup timer at EL1 level and not able to write to CNTP_CVAL register.

    I would like to know what is the meaning of "Config-RW"  ? It means can be configured ? eg. to be accessed from (NS) EL1 mode ?

    If so what/how to configure…

  • Issue with eret

    Hi,

    I am doing "eret" from EL2h mode and expecting that I should jump to EL1h mode but rather it is taking me to EL0t mode.

    I am trying to root cause the issue but not able to figure out. Any pointers will be helpful ?

    Thanks

  • How to check Cache DATA view for Juno

    Hi,

    I am trying to check cache line for an address by connecting Juno with DS-5 but I get "No tables available".

    I also changed DTSL configuration editor settings by enabling both options bust still can not see any thing.

    I also tried running directly…

  • Issue compiling ARMv8 assembly

    Hi,

    I am using "gcc-arm-none-eabi-4_9-2015q1" to compile ARMv8 - A53/A57 code and getting following errors while compiling assembly files -

    I am giving -march='armv8-a' option. I am not sure how to resolve this ?

    Assembler messages:
    Error…

  • ARMv8 backwards compatibility with ARMv7

    Hi there,

    I have been going through a lot of ARMv8 documents, and I have a very basic question:

    -Can I take a Linux Kernel, compiled for a ARMv7 device, and run it on an ARMv8 device in Aarch32 execution mode?

    ( Lets assume that the two SOCs are identical…

  • the UART char print in ARM v8-A Foundation Platform

    Hi All,

    I am using ARM v8-A Foundation Platform to debug my code. According to user guide, the base address of UART0 in system is 0x1c090000, so I use the following code to try to print a char via UART0:

    *(volatile unsigned char *)(0x1c09000 + offset_of_tx_fifo…

  • how to understand ARMv8 exception level1 secure/non-secure MMU?

    Hi Experts,

         ARMv8 MMU TTBRn_ELx registers are banked by exception level.

         In "DDI0487A_b_armv8_arm.pdf" page 1640, the controlling register of secure EL1&0 stage1 is TTBR0_EL1

         and Non-secure…

  • Is Juno Board suitable for ARM BSP development?

    We are interested in developing Board Support Package and Bootloader code for SOCs based on ARMv8 Architecture (A57/A53). Can someone please suggest is Juno Board a good option for it?

    We are interested in writing the BSP code for Memory Controller, UART…

  • ARM Trusted Firmware, number of cpu cores..

    Hi all,

    I have two questions about ARM Trusted Firmware. I suppose that I already have answer for one of them..

    1. Does Trusted Operating System (at Secure EL1) use or can use, more than one cpu core, or it always executes on one core?
    2. Does bl31, runtime firmware…
  • How to understand ARMv8 'SEVL' instruction in spin-lock?

    hi experts,    

        ARMv7 spin-lock use 'WFE' instruction to wait for lock release and use 'SEV' in spin-unlock to notify all cores.   

        but ARMv8 use 'SEVL; WFE' instructions in spin…

  • Purpose of EL0 EL1 ..

    Hi all,

    ARMV8 has number of exception levels as EL0 , EL1, EL2, EL3 .. How this is managed and what is the exact use case of the same ?

  • Generic Timer - Is it optional?

    Hi all,

    The generic timer feature is provided in the V8 manual. Is it optional like GIC or it will be available with processor IP by default like cache, MPU features. Is it operates on CPU clock or it requires separate clock source ?