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Hi everyone ,

I'm currently using a Cortex-A9 processor (NXP Freescale i.MX6S).

My project is to develop a simple OS, but I met a problem:   

When I am trying to control some peripherals (such as UART and GPIO) directly under ARM USER MODE, the program…

Hi,

I am experimenting execution level switching on A53. I go from EL3->El2, then call SMC instruction to return to EL3. As soon as SMC instruction is executed, the processor enters EL3 mode and an exception is generated.

I have written an exception…

Hi,

I'm using a Juno r1 board and I'm trying to get processor's related CPU ID without using any header file like function sched_getcpu from sched.h.

The reason is I want to get the CPU number for TrustZone application and there is no way to…

Hello experts,

I have come to having a question.
VFP Benchmark is a benchmark application which was made by a certain Japanese in order to measure ARM VFP performance especially for ARMv7-A and ARMv8-A.
The software can be downloaded from the following link…

Hi experts,

I want to knows why there are 4 core cores per cluster in ARM big.Littte architecture?

Is it possiable if we make more cores per cluster? if not, what is the limitation?

I find the description below from MMU-500 TRM.

Address width

The incoming address width is fixed at 49 bits, where A[48] specifies VA sub-ranges. You must tie all unused bits to zero. The output address width is 48 bits and the width of the AC address

bus…

Say, like Time Stamp Counter of x86, or Time Base of PowerPC, which can used to

do some performance profiling.

Where can i get a list of all these family of ARM processors and their differences

On ARMv7 Cortex-A8/9/7, to map 4GB memory space, the minimum MMU table size is 16 KB(section mapping). Any possible to map 4 GB memory space with 16 KB MMU table, on ARMv8, AArch64 mode?

Two questions:

1. Where can I find the detailed explanation of ARM PMU events?

2. How to know the stall cycles for e.g. icache miss etc.?

Thanks.

Hi, ARM experts:

    When we porting a secure os in 32bit mode in v8 secure EL1(our EL3 is running in AARCH 64bit mode), we got a strange problem:

    When start booting secure os in secure EL1, the bootstrap code…

Hi, arm experts,

We want to use ARCH32 mode in secure EL1, I see some descriptions in ARMv8 Arch Reference Manual about Secure EL1 ARCH32 mode as follows:

One is the VBAR(secure), it is mapped to  VBAR_EL3, the other is SCTLR (secure), it is mapped to …

I read TZ whitepaper. TZ's software architecture includes normal OS, secure OS, and a monitor that manages switching between two OS. The notion is clear. But how to implement them confuses me.

Running and managing two kernels on a SoC needs mechanism…

Now I use DS5 to develop an assembly crypto code, instructions like AESE are used in my code, after assign the CPU = 8-A.64.crypto, the code could be built, but when i debug the code in

the FVP VE_AEMv8x1, the program crash, do anybody now how to use instructions…

I am reading SMMU spec V2.0, and wondering why no C bit in SMMU_CBn_SCTLR. There is M bit in it.

There is a system with two CPU,for example,cpuA and cpuB. Firstly, cpuA issue a LDREX for accessing the address A,and cpuB issued a STORE for writing the address A. If CPUA send a STREX for writing the address A after the Store issued by cpuB。 I notice…

Hi,

I am facing "Bus error on memory operation" while executing below instruction while invalidating and flushing the TLB.

I am not able to understand what is the reason for "Bus error" as it is a TLB operation instruction ?  Also what Bus error…

In ARM7 and ARM9 PC=current + 8, but in the cortex-A7(8-stage pipeline) the PC is also the same value(PC=current +8), how does this work?

I think the cortex-A7 has 8-stage pipeline, the PC value is also current+8(this is back-forward for old design), but…

Hi,

I was using following method to read clock in cortex-a15:

       static void readticks(unsigned int *result)

        {

            struct timeval t;…

Hi Experts,

I'm reading white paper for ARMv7 and ARMv8.

but when i reading cache part and memory re-ordering, i have silly questions.....

Suppose there are below instructions..

Core A:

     STR R0, [Msg]

     STR R1, [Something…

Hello Community,

I am currently learning hypervisor design using ARM's virtualization extensions (on both ARMv7 and ARMv8).

A note in the ARMv8-A reference manual (section D1.5) mentions:

"In some systems, a Guest OS is unaware that it is running on…

Hi,

    I am working on bootloader porting to ARM v8 platform. I am facing a problem in enabling MMU in execution level-1 EL1.

I am not able to set sctlr_el1.M bit when ever i try to set this bit the instruction won't complete. I think it…

Hi experts,

     i am trying wakeup the secondary CPU core in bootloader, i am able to do this through a trusted firmware. The problem comes after wakeup!

Once the cpu is up it will be in EL-2 mode and it executes a predefined function…

Hi Experts,

                    I was going through the arm v8 mmu page table formation, when it's compared to arm v7 it is completely different.

I could…

GIC-500 how connects to CPU cores?

在GIC-500 中CPU Interface 是GIC的一部分还是cluster 的一部分？