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I have a basic concept question.  From what I read in the ARMv8 docs... there is an NS and NSTable bit in the page table entries themselves for the 2nd level and higher page table lookups.  So these can be used to block access ... I.e. NS access is attempting…

Hi,

I'm using DMA transfering data through ACP on A53. 

According to A53 TRM, ACP burst size limits to 16B and 64B, does it mean the DMA connect to ACP also limited to transfer 64B data in max each time?

Then software must re-configure DMA then re…

HI,

Do anyone has a clue on the latency of the MRS CPSR (or APSR) command?

I want to read the flags with no jump (and it is critical).

Thanks

Hi, 

I have board with two clusters, one has 4*A57 cores, and the other has 4*A53 cores.

The A57 cluster has its own L1 and L2 cache, A53 cluster also has its own L1 and L2 cache. Between the clusters there is a CCI.

There is no L3 cache. So the memory…

We are developing a bare metal secure OS on a NXP LS1043a board, with a Cortex A53 v8 core.

While debugging some issue with DMA, I decided to switch all kernel mapping from Normal cacheable to Strongly ordered (Device-nGnRnE memory type) and then witness…

excuse me for my English!!!

i want to write bare-metal startup code in 32-bit mode for LS1043A-Rdb.it is having V8 A53 core.

i have bare-metal 32bit(AARCH32) code for xilinx processor(which is of V8,A53core).How much of that code is useful to write code…

******************************************************************************/
/*****************************************************************************/
/**
* @file translation_table.s
*
* @addtogroup a53_32_boot_code
* @{
* <h2> translation_table…

can you please tell me how to boot up a processor in 32 bit mode for Armv8, A53 core using baremetal code?

how can i know it is booted in 32bit mode?

Thanks.

Where is the register definition of the CurrentEL register ?. I cannot seem to find it in the ARMv8A programming model guide or the Cortex-A53 TRM.

. How does the PSTATE bits map to CurrentEL ?

I read somewhere that a CurrentEL value of 0x4 denotes EL1…

Hi,

ARMv8-A specification mentions revisions and options. I cannot find Cortex-A35 adheres to which exact version: ARMv8.1, 8.2, 8.3? I want to know which of the extensions described in the generic ARMv8-A spec are really available in that core.

Thanks…

Dear experts,

 I'm going to implement multi-core(4 cortex-a53) in my private OS. I have an issue which needs your confirmation.

Q. When core0 invalidates the L1-cache and L2-cache at VADDR(Cached), Can other cores  get the right data at VADDR ?

For…

Please clarify that with me... With

"The current Program Counter (PC) cannot be referred to by number as if part of
the general register file and therefore cannot be used as the source or destination
of arithmetic instructions, or as the base, index…

Hi Experts,

Please specify is there any document on the Cortex A series comparison sheet for the various properties.

For example, Table 2.1 in the https://static.docs.arm.com/den0024/a/DEN0024A_v8_architecture_PG.pdf has details on A53 and A57. Likewise…

I come across strange issue with Optimization setting O2 and O3 option my code will not work due to PC corruption, with O1 and O0 code woke fine, our target procesor is Arch64bit Cortex-A53. how to fix this issue. my i know what is the limitation of Heap…

Hi,

I've heard that the cost of implementing a register is more.

In ARMv8 there is a Zero register XZR/WZR, so what is the benefit of implementing such a register over the cost of implementing it?

The technical spec for ARM Cortex A-75 claims that it supports a full implementation of ARMv8.2-A. The documents I have been able to reference only point to ARMv8A. Specifically I'm looking for what ARMv8.2-A brings to the SIMD table other than fp16 arithmetic…

Is there a way to update the PC register in the aarch64 mode?

When we are at aarch32, we can access PC register directly. But in aarch64 mode, there is no handle to PC register.

Hi all:

I have some questions about DMB and DSB in armv8.

(1)

In armv8 Reference Manual doc, it says "The DMB instruction does not ensure the completion of any of the memory accesses for which it ensures relative order".

But in ARM Cortex-A…

Hi everyone,

Wherever I go on internet, the thing I read is that when SMC instruction is executed an exception is generated, it takes you to the highest exception level (EL3) where secure monitor is running.

In ARM v8 vector table, given on ARMv8-A architecture…