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  • Updating PC register in aarch64 mode

    Is there a way to update the PC register in the aarch64 mode?

    When we are at aarch32, we can access PC register directly. But in aarch64 mode, there is no handle to PC register.

  • MMU - Permission Fault with EL1 access

    Hello everyone,

    I'm trying to wrap my head around the MMU configuration for Cortex A53 armv8 architecture (AArch64). Specifically, I'm programming for Raspberry Pi 3 (Bare Metal).

    I've successfully setup the page tables for two levels covering…

  • TTBR1 translation fault when using an identity mapping

    Hello everyone,

    I'm experimenting a bit with MMU after understanding its core principles. Specifically I can successfully enable it with an identity mapping for TTBR0 (no TTBR1) on a Raspberry Pi 3 (Cortex A-53, ARMv8 AArch64).

    The next step I wanted…

  • code is not working for optimization setting O2 and O3 for Arch64bit Cortex-A53 process

    I come across strange issue with Optimization setting O2 and O3 option my code will not work due to PC corruption, with O1 and O0 code woke fine, our target procesor is Arch64bit Cortex-A53. how to fix this issue. my i know what is the limitation of Heap…

  • Armv8-A architecture: 2016 additions

    The Armv8-A architecture continues to evolve, with the additions developed through 2016 collectively known as Armv8.3-A. Grouping enhancements in this manner helps the ecosystem manage tools and software support alongside the large numbers of Armv8-A…

  • TTBR1_EL1 aligment

    Hi !

    I'm struggling a bit to understand the alignment constraints on the physical address we put in TTBR1_EL1. The ARM ARM v8 doesn't give a precise link in TTBR1_EL1 description to where is alignment is defined. For this post, I'm using a 4k granule…

  • Getting ERROR "unknown mnemonics for UQSUB8 instruction"

    Hi community,

    I have tried to compile the source code for openVG
    I have given proper cross compiler which is required by the platform still I am getting the error of unknown mnemonics for the instruction UQSUB8

    Environment:

    - Linux platform

    - CROSS COMPILE…

  • Is it possible to implement EL3 AArch64 and change it later to EL3 AArch32?

    I was reading the ARM architecture reference manual... and thought

    Is it possible to implement EL3 AArch64 and change it later to EL3 AArch32?

    How to change is...

    If I start on cold reset, it will start at EL3 AArch64.

    Right after the cold reset, I set the…

  • Armv8-A architecture evolution

    Armv8-A adoption continues to grow as the demand for 64-bit computing gathers momentum. As reported in the Q3-2015 financial results, Arm has now signed a cumulative total of 81 Armv8-A processor and architecture licenses, an increase of 24 licenses in…

  • Programmer's Guide for ARMv8-A

    Following on from the popularity of the Cortex-A Series Programmer’s Guide for ARMv7-A, there is now a programmer's guide for processors implementing the ARMv8-A architecture profile.

    The new Cortex-A Series Programmer's Guide for ARMv8-A…

  • ARM Shares Updated Cortex-A53/A57 Performance Expectations

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    With the first Cortex-A53 based SoCs due to ship in the coming months, and Cortex-A57 based designs to follow early next year, ARM gave us a quick update on performance expectations for both cores. Given the timing of both designs we'll see a combination…