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  • how to return from exception generated by SMC instruction

    Hi,

    I am experimenting execution level switching on A53. I go from EL3->El2, then call SMC instruction to return to EL3. As soon as SMC instruction is executed, the processor enters EL3 mode and an exception is generated.

    I have written an exception…

  • how to understand ARMv8 exception level1 secure/non-secure MMU?

    Hi Experts,

         ARMv8 MMU TTBRn_ELx registers are banked by exception level.

         In "DDI0487A_b_armv8_arm.pdf" page 1640, the controlling register of secure EL1&0 stage1 is TTBR0_EL1

         and Non-secure…