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  • EDSCR err bit set after a write to EDITR

    Hi,

    I have a very similar question to the resolved entry "reason for ARMv8 EDSCR err bit set".

    So I try to follow that to give the state information.

    Cortex-57

    JTAG TCK = 3,788MHz.

    ARM_STATE_AARCH64 is set

    Before Halt state:

    EDPRSR = 0x1

    EDSCR…

  • How to measure program execution time in ARM Cortex-A53 processor?

    Hi,

    I was using following method to read clock in cortex-a15:

           static void readticks(unsigned int *result)

            {

                struct timeval t;…

  • Confusion about exception level of ARMv8

    Hi,

    I am fairly new to ARM processor and start work with cortexA57 recently.  After reading the technical manual and programmer guide , I have some questions regarding the exception level of v8.

    1. How does the exception level change from one to…

  • ARM Shares Updated Cortex-A53/A57 Performance Expectations

    1.jpg

    With the first Cortex-A53 based SoCs due to ship in the coming months, and Cortex-A57 based designs to follow early next year, ARM gave us a quick update on performance expectations for both cores. Given the timing of both designs we'll see a combination…