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  • Differences between Privilege Modes and Non-Privilege Mode ?

    Hi everyone ,

    I'm currently using a Cortex-A9 processor (NXP Freescale i.MX6S).

    My project is to develop a simple OS, but I met a problem:   

    When I am trying to control some peripherals (such as UART and GPIO) directly under ARM USER MODE, the program…

  • how to return from exception generated by SMC instruction

    Hi,

    I am experimenting execution level switching on A53. I go from EL3->El2, then call SMC instruction to return to EL3. As soon as SMC instruction is executed, the processor enters EL3 mode and an exception is generated.

    I have written an exception…

  • Why does FPU performance differ in AArch64 and AArch32 with Cortex-A53?

    Hello experts,


    I have come to having a question.
    VFP Benchmark is a benchmark application which was made by a certain Japanese in order to measure ARM VFP performance especially for ARMv7-A and ARMv8-A.
    The software can be downloaded from the following link…

  • Minimum MMU table size on ARMv8 to map 4GB memory space, in AArch64 mode

    On ARMv7 Cortex-A8/9/7, to map 4GB memory space, the minimum MMU table size is 16 KB(section mapping). Any possible to map 4 GB memory space with 16 KB MMU table, on ARMv8, AArch64 mode?

  • How to measure program execution time in ARM Cortex-A53 processor?

    Hi,

    I was using following method to read clock in cortex-a15:

           static void readticks(unsigned int *result)

            {

                struct timeval t;…

  • shareable attribute in armv8

    Hi Experts,

                        I was going through the arm v8 mmu page table formation, when it's compared to arm v7 it is completely different.

    I could…

  • indirect branches in ARMv8

    Please clarify that with me... With

    "The current Program Counter (PC) cannot be referred to by number as if part of
    the general register file and therefore cannot be used as the source or destination
    of arithmetic instructions, or as the base, index…

  • which register are dedicated for each MPCore in ARMv8-A architecture?

    Hi  Expert,
    I'm a beginner to ARMv8-A architecture MPcore and now studying A35 MPCore processor documents for low-level software developing.
    One question, when I read DDI0487C_a_armv8_arm and DEN0024A_v8_architecture_PG, from my understanding, there…

  • code is not working for optimization setting O2 and O3 for Arch64bit Cortex-A53 process

    I come across strange issue with Optimization setting O2 and O3 option my code will not work due to PC corruption, with O1 and O0 code woke fine, our target procesor is Arch64bit Cortex-A53. how to fix this issue. my i know what is the limitation of Heap…

  • Confusion about exception level of ARMv8

    Hi,

    I am fairly new to ARM processor and start work with cortexA57 recently.  After reading the technical manual and programmer guide , I have some questions regarding the exception level of v8.

    1. How does the exception level change from one to…

  • Advantage of Zero register over the cost of implementing it ?

    Hi,

    I've heard that the cost of implementing a register is more.

    In ARMv8 there is a Zero register XZR/WZR, so what is the benefit of implementing such a register over the cost of implementing it?

  • Updating PC register in aarch64 mode

    Is there a way to update the PC register in the aarch64 mode?

    When we are at aarch32, we can access PC register directly. But in aarch64 mode, there is no handle to PC register.

  • Programmer's Guide for ARMv8-A

    Following on from the popularity of the Cortex-A Series Programmer’s Guide for ARMv7-A, there is now a programmer's guide for processors implementing the ARMv8-A architecture profile.

    The new Cortex-A Series Programmer's Guide for ARMv8-A…