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  • Updating PC register in aarch64 mode

    Is there a way to update the PC register in the aarch64 mode?

    When we are at aarch32, we can access PC register directly. But in aarch64 mode, there is no handle to PC register.

  • MMU - Permission Fault with EL1 access

    Hello everyone,

    I'm trying to wrap my head around the MMU configuration for Cortex A53 armv8 architecture (AArch64). Specifically, I'm programming for Raspberry Pi 3 (Bare Metal).

    I've successfully setup the page tables for two levels covering…

  • dsb and dmb

    Hi all:

    I have some questions about DMB and DSB in armv8.

    (1)

    In armv8 Reference Manual doc, it says "The DMB instruction does not ensure the completion of any of the memory accesses for which it ensures relative order".

    But in ARM Cortex-A…

  • Help configuring PMU's

    Hi,

    I'm trying to enable PMU's on arm versatile juno r2 development board.

    I've already read this manuals from arm:
    ARM ® Cortex ® -A72 MPCore Processor
    ARM® Cortex ® -A53 MPCore Processor
    Juno r2 ARM® Development Platform SoC…

  • Trap translation fault at EL2

    it is only possible to trap only translation fault to el2 in armv8-A ?

  • aarch64 MMU: inconsistency in ARMv8 ARM?

    Hello,

    I try to reconfigure the MMU of an existing project. I try to do this by building upon an example of ARMv8 ARM. The example is the one in section K7.1.2, fig. K7-11, page 7293.

    I find the information in ARMv8 ARM to be conflicting. In fig. K7-11…

  • Enable MMU and d-cache on ARMv8 for u-boot

    Hi,
    This question is for MMU and d-cache. When I tried to enable MMU and d-cache for u-boot I ran into Synchronous Abort handler while writing to PCIe device registers which I mapped as uncached memory. The dump is shown below
    "Synchronous Abort" handler…

  • TrustZone environment for ARMv8-M?

    I want to work the TrustZone program for ARMv8-M.
    Is there TrustZone environment for ARMv8-M? (ex. software emulator.)
    I used Foundation_Platformpkg for ARMv8-A.
    Similar environment is available?

  • Correct way to mask interrupts in secure world ARMv8M M33

    Hello,

    I'm wondering what the correct way to mask non secure interrupts is, on entering secure world on an ARMv8-M processor, with Main and Security extensions. The scenario I have is as follows:

    The SOC has 1 M33 core. I have a non secure OS that…

  • How to run TF-M on keil M23/M33 fvp?

    I have noticed there are also M23/M33 fvps  under Keil IDE related path. Whether there is some difference about the startup parameters to run TF-M on Keil fvps compared to DS-5  fvps?

  • Porting PuTTY to Windows on Arm

    In my day job, I work in the Arm Development Solutions Group, developing Arm Compiler and its supporting tools. In my spare time, I’m also the lead developer of the free SSH client PuTTY.

    Recently, Windows on Arm has been making a splash, so last…

  • ARMv8-A: Virtual to physical translation sometime "fails"

    Hi

    I have a strange effect: I need to convert a virtual address to the physical one.

    In the current scenario, I have a 1:1 mapping, so I would not need it, but left the code:

    	mov	x3,x0  // for debug
    	at	S1E1W,x0
    	isb
    	mrs	x1,PAR_EL1
    	mov	x4,x1 /…

  • No segmentation fault when expected with aligned load and store

    Hi all,

    It is a well known fact that performing an aligned vector load with an unaligned memory address should lead to segmentation fault.

    However, when I do try to run code segment below using the same, i do not see any segmentation fault.

    ---------…

  • Devboards or FVP which have support for ARM v8.5A ?

    I was wondering if anybody is aware of any devboard/FVP which contain features introduced in ARM v8.5A such as memory tagging? 

  • TTBR1 translation fault when using an identity mapping

    Hello everyone,

    I'm experimenting a bit with MMU after understanding its core principles. Specifically I can successfully enable it with an identity mapping for TTBR0 (no TTBR1) on a Raspberry Pi 3 (Cortex A-53, ARMv8 AArch64).

    The next step I wanted…

  • Emulating SVE on existing Armv8-A hardware using DynamoRIO and ArmIE

    The Arm Instruction Emulator (ArmIE) is a tool that converts instructions not supported on hardware to native Armv8-A instructions, such as those from the Scalable Vector Extension (SVE) instruction set. ArmIE enables developers to run and test SVE binaries…

  • Advantage of Zero register over the cost of implementing it ?

    Hi,

    I've heard that the cost of implementing a register is more.

    In ARMv8 there is a Zero register XZR/WZR, so what is the benefit of implementing such a register over the cost of implementing it?

  • NE10 和 acl(arm compute library)那个效果更好?

    现在想优化arm cpu 的运算能力,看到这两个库 ne10 和ACL,如果只针对cpu(比如A9和A53),那个库的运算性能更好?

    题外话,NE10和ACL 的定位和区分度?

  • Arm A-Profile Architecture Developments 2018: Armv8.5-A

    Working with its architecture licensees and ecosystem partners, Arm continues to evolve its architecture, developing new functionality to meet the needs of both new and existing markets.

    This blog discusses some of the key additions to the A-Profile architecture…

  • Statistical Profiling Extension for ARMv8-A

    The Statistical Profiling Extension is an optional feature in ARMv8.2. This article will provide an overview of the Extension, describe how it works, and the advantages it provides over other profiling mechanisms.

    Recently, Will Deacon posted a request…

  • Porting to Arm 64-bit

    This white paper is an introduction to porting existing code to the A64 instruction set supported by Armv8-A processors like the Cortex-A53 and Cortex-A57 from Arm. It will also be useful for those writing new code for these platforms.

    Why 64-bit?

    Diagram of evolution of Arm architecture

  • Which ARMv8 register controls cache partitioning

    Hi ARM folks,
    Which register controls the cache partitioning behavior on ARMv8 chips?
    My group is working with a Cavium ThunderX, and we're trying to experiment with different cache partitioning schemes. ThunderX are ARMv8 chips, as mentioned here…
  • What ARMv8.x revision Cortex-A35 is?

    Hi,

    ARMv8-A specification mentions revisions and options. I cannot find Cortex-A35 adheres to which exact version: ARMv8.1, 8.2, 8.3? I want to know which of the extensions described in the generic ARMv8-A spec are really available in that core.

    Thanks…

  • Arm Allinea Studio 18.3 is now available with new math routines and FFT improvements

    Arm Allinea Studio 18.3 is now available with updated Arm Performance Libraries and improved compilers.

    Math routines - pow, exp, and log - now part of Arm Performance Libraries

    Arm Performance Libraries 18.3 includes a new library libamath, with optimized…