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Hello,

I am trying to make pmd level of the translation table as read only so that any writes in the pte entries should cause a permission fault.

Current steps which i am doing are:

1) inside kernel space, allocating 2 pointers (say p, q) and allocating…

Hello 

I'm working on the Bootloader stage (EL2), I'm trying to enable Interrupts with gic v3 in that stage

I've enabled routing IRQ, FIQ and Aborts from EL0, EL1 and EL2 to EL2  using these piece of code 

MRS X0, HCR_EL2
AND X0, X0, 0xFFFFFF…

Is the FVP accurate in terms of measuring performance of programs? Is it cycle accurate? If I use clock_gettime to measure time taken on applications, is it meaningful? If not, is there an accurate way to measure performance of programs on the FVP?

Hello,

I was trying to configure the MPAM system for cache capacity partitioning utilising the fvp base model. I noticed, reading the comments related to the configuration parameters, that the maximum capacity control is not functional, but, anyway, the…

Hello,

I'm working with i.MX8DX (Dual Core CortexA35 + CortexM4) with the following simplified caching system:

My need is to flush a cached memory area to RAM in order to be viewed by the M4 core, unfortunately this area maybe cached by Core 0 and…

Greetings,

I would like to enable top-byte ignore support on the FVP. I would be grateful on any guidelines on how to do that. Thank you very much!

Best regards,

Mohannad Ismail

Greetings,

If I leave the FVP idle for around 1 hour and come back to it, I find that it freezes and have to stop the simulation and re-run it again. What is the possible reason for this and is there a way to stop that from happening? Thank you for your…

Hi,

I am currently working on an integrity enforcer running in a modified version of the ARM trusted firmware in EL3. To gain access to the memory I added 4 1GiB entries to the translation tables located in the TTBR0_EL3.

Now I am trying to hook the pagefault…

Hello,

I would like to know how do I attach gdbserver to my ARM Base FVP for debugging. All tutorials online explain using DS-5. I would like to use gdb since I am more comfortable with it. I already enabled networking on my FVP.

Thanks for your help…

Hello. I am a novice in programming. I have a problem with the debugger.
My target CPU is Cortex-A72 Aarch64, FPU Armv8 (Neon). I use vectorization.
When the debugger reaches the line:
uint8x16_t aa = vmovq_n_u8 (0);
he writes that it is running, but nothing…

Hello,

I would like to know how do I attach gdbserver to my ARM Base FVP for debugging. All tutorials online explain using DS-5. I would like to use gdb since I am more comfortable with it. I already enabled networking on my FVP.

Thanks for your help…

Hello, 

I am a PhD student doing research using the ARMv8 hardware features. I have a few questions regarding them. Some of these may seem a bit trivial, but I like to be a bit more thorough and confirm my understanding, and ARM is relatively new to me…

The DCIMVAC represents a cache invalidate work. But one specific remark is that it will clean the data if the data is dirty before invalidation. Refer to followings

/******************************************************/

6.2.4 Data cache maintenance…

Hello,

I want to use the ARM pointer authentication feature. I compiled a program with PAC instructions. I inspected the assembly and made sure they were properly inserted. I also compiled and ran an ARM Base FVP and was able to share the directories…

最近在阅读ARMv8的技术手册，有一个细节问题没有搞明白，请各位高手指点，谢谢！

文档Cortex-A Programmer‘’s Guide里说，AArch32的SVC模式下，SPSR寄存器映射到SPSR_EL1。

问题是，如果处理器的EL3以AArch32状态运行，则安全态没有EL1，只有EL0和EL3，SVC、IRQ等模式都在EL3实现。那么此时处理器在安全态的SVC模式下运行时，SPSR寄存器是否还是映射到SPSR_EL1？monitor模式的SPSR寄存器用的是否是SPSR_EL3…

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Hello,

I'm working with a bare-metal application running on i.MX8 (QuadCore CortexA35 & Single Core CortexM4).

Currently, I use Load/Store executive assembly instructions along with memory attributes for the MMU to synchronize between the CortexA…

Hi all - I'm trying to understand stage 1 translation.

Assuming that the translation is starting at level 2, how do you determine the number of page table entries in the level 2 table? The documnetation says it can have up to 512 for 4kb granule size…

I am using ARMv8 GCC compiler(aarch64-none-elf-gcc) for my bare metal application on ARM cortex a53. I am using neon intrinsics with plain C in my code so I would like to ensure to use all optimization option available for this compiler.

I tried -mfpu…

Hello,

I am working with a port of FreeRTOS on Arm64 soc , which is running at EL1, my goal is to perform a function call that will execute in EL0,

I have come to understand that the only way for the EL switch is to set the correct M bits of the spsr_el1…

Hi all,

I am working on UltraZed-EG Starter Kit and trying to boot secondary A53 core from primary A53 core with an SMC call with 0xc4000003 as the identifier. I have measured the time taken to reach the entry point of secondary core and surprisingly…

Is it possible to have a normal store operation between LDX and STX operations from the same core/master?

Hi ARM folks, hoping someone can show me where I'm going wrong programming the MMU. The ESR_EL1 reports that it is a Permission fault, level 2. Here's what I'm trying to accomplish:

4GiB space, 4kiB granule flat identity mapped, divided like…

Dear experts,

I see a lot of code in opensource like

.macro disable_daif
     msr     daifset, #0xf
.endm


and it doesn't apply ISB instruction after it. Though I read in ARM manual that:
"context-changing operations
that require the insertion…