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  • CORTEX-A processor interrupt handling

    Since I am currently reading lot of ARM documents to understand the architecture as a whole, I request you to mention as to what happens in case of CORTEX-A processor in the nested interrupt handler implementation since we have a SPSR in CORTEX-A processors…

  • Performance effect because of removing some instructions from ARMv8?

    I was going through the ARMv8 Architecture Reference Manual and I came to know that it does not support many instructions that were previously supported by ARMv7 architecture. For example ARMv8 does not support conditional codes and have a seperate instruction…

  • ARM Zynq Cortex-A53: implementing complex matrix inversion

    Hello,

    I am developing embedded software on Zynq MPSOC Cortex-A53 (Armv7/Armv8) for image processing, and I need some help for developing a specific algorithm.

    The algorithm involves many calculations of FFT and matrix using. As highest priority, we…

  • Branch Predictor detailed info

    Hi all,

    Is there any document related to the branch predictor algorithm utilized in the ARMV7 and ARMV8 and how the software (ABI) can be aptly developed ac-complying the same ?

  • Critical interrupts

    In software there are often cases where you need to have critical interrupts serviced. For example, for:

    • Code profiling
    • Kernel debugging
    • Watchdog handling
    • Error handling.

    With the ARMv7-M architecture this can be achieved using nested interrupt handlers, but…