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  • Exceptions levels in the ARMv8 architecture

    Hello

    There are four exceptions levels in the ARMv8 architecture.

    EL0
    EL1
    EL2

    EL3

    Can anyone explain more of the EL3 execption level? What does it mean by 'allows swtiching between secure and nonsecure processor states? Secure monitor?

    Thanks

  • is it necessary for ARM-v8 soc to flush L2 cache to DRAM ?

    hi :

    I know , we can flush L1 I/D cache items to PoU with kernel interface(flush_cache_*).

    however, I can not find any clue about flushing L2 cache to DRAM(if without L3). 

    and I saw some points that L2 flushing was not needed.

    for ARMv8,  how can…

  • Introducing 2017’s extensions to the Arm Architecture

    Introduction

    The Arm Architecture is continually evolving, and this blog gives a high-level overview of some of the changes made in Armv8.4-A*. We develop these changes by listening to the Arm Ecosystem and working with them to provide new functionality…

  • Issue with stxr in ARMv8

    Hi,

    I am writing a simple spinlock taking Juno arm trusted firmware spinlock code.

    But for me stxr instruction is always failing giving w1 value as "1" always.

    When I read ARMv8 spec it says (under section B2.10.5) "Unpredictable behavior when…