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  • Transition to secure monitor flow on ARMv8

    Hi everyone,

    Wherever I go on internet, the thing I read is that when SMC instruction is executed an exception is generated, it takes you to the highest exception level (EL3) where secure monitor is running.

    In ARM v8 vector table, given on ARMv8-A architecture…

  • Transition to secure monitor flow on ARMv8

    Hi everyone,

    Wherever I go on internet, the thing I read is that when SMC instruction is executed an exception is generated, it takes you to the highest exception level (EL3) where secure monitor is running.

    In ARM v8 vector table, given on ARMv8-A architecture…

  • How to know if the processor is in EL0 state on armv8?

    Hi Fellows,

    I want to determine in code, if the processor is in EL0 mode or not. I read CurrentEL register to do this but if my code is running from EL0, it throws an exception since we can't access CurrentEL from EL0. Is there any alternative and easy…

  • Is any synchronization barrier instruction necessary after writing SPSel to switch to SP0 on armv8?

    Hi Fellows,

    I want to switch stack pointer to SP0 from SP1 every time an exception is taken to EL1 on armv8. I execute MSR  SPSel, #0 to do this. My question is that is it necessary to use an ISB intruction etc. after it? If yes, what are the performance…