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Since I am currently reading lot of ARM documents to understand the architecture as a whole, I request you to mention as to what happens in case of CORTEX-A processor in the nested interrupt handler implementation since we have a SPSR in CORTEX-A processors…

Hi,

I'm working on a project which is for debugging cortex-a53 through Jtag interface.

The Jtag clock TCK is set to 300kHz which is pretty low, and I can properly read back debug registers such as EDSCR and EDPRSR. EDPRSR is 1 before I issue the 'halt…