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  • Build a Buildroot user-space

    Preface

    This article outlines how to build a custom root filesystem with Buildroot to use on Armv8 FVP's. More specifically the article discusses:

    • How to install and configure Buildroot. (PART I)
    • The process of creating a usable filesystem image…

  • Juno Software Binary Images

    Juno software deliverables are now hosted by Linaro. (The deliverables previously available on the Arm Community are obsolete and have been removed).

    Instructions for using the Linaro software deliverables

  • Boot an arm64 kernel on the Juno r1 platform

    Using the default firmware shipped with the board. Plus:

    • Git the arm64 kernel tree
    • Build the kernel with arm64 tool chains:

    # export ARCH=arm64
    # export CROSS_COMPILE=aarch64-linux-gnu-
    # make defconfig
    # make -j8 Image

    Copy the 'Image' generated in…

  • Modify Linux kernel config flags in the Arm Platforms deliverables

    Preface

    This article:

    • Compares how an upstream kernel.org kernel is built and how an Arm Platforms deliverables kernel is built.
    • Describes how to enable/disable arbitrary kernel config flags for an Arm Platforms deliverables kernel.

    These instructions…

  • how to build an arm juno r1 application from an linux platform

    The toolchain of my linux computer is x86_64-redhat-linux.

    On Juno board, I run the prebuilt image https://releases.linaro.org/openembedded/juno-lsk/15.09/lt-vexpress64-openembedded_minimal-armv8-gcc-4.9_20150912-729.img.gz

    1. I searched online, many developers…

  • How to get the secure(or non-secure) state on Cortex-A53?

    Could anyone give me the code to get the current secure state?

  • why some instructions are not required to be  explicitly synchronized ?

    Dear all:

    In "ARM® Architecture Reference Manual ARMv8", B2.6.5 Concurrent modification and execution of instructions ,

    it says some instructions, such as " B, BL, NOP, BRK, SVC, HVC, and SMC " dont need to be explicitly synchronized to…

  • CORTEX-A processor interrupt handling

    Since I am currently reading lot of ARM documents to understand the architecture as a whole, I request you to mention as to what happens in case of CORTEX-A processor in the nested interrupt handler implementation since we have a SPSR in CORTEX-A processors…

  • What is the difference of DMB and DSB instruction?

    Dear sirs,

    From the specification from ARM architecture, DMB needs to make the load and store operation before DMB instruction have an explicit ordering. However, the description of DMB is a loop which is very difficult to understand.

    DMB only cares about…

  • Exceptions levels in the ARMv8 architecture

    Hello

    There are four exceptions levels in the ARMv8 architecture.

    EL0
    EL1
    EL2

    EL3

    Can anyone explain more of the EL3 execption level? What does it mean by 'allows swtiching between secure and nonsecure processor states? Secure monitor?

    Thanks

  • How to deice debug target exception level of watchpoint on ARMv8 architecture

    Hello, everyone

    I'm new to this community.

    I'd like to ask many questions and want to help someone.

    Now I have some difficulties in understanding aarch64's watchpoint exception handling scheme.

    I found I can decide which exception level whachpoint…

  • Foundation Model for ARMv8

    Hello. I am using ARMv8 foundation model for my project. When configure foundation model with multi cores (cores=4) my code does not run. Can you lease help me solve this problem?

  • is it necessary for ARM-v8 soc to flush L2 cache to DRAM ?

    hi :

    I know , we can flush L1 I/D cache items to PoU with kernel interface(flush_cache_*).

    however, I can not find any clue about flushing L2 cache to DRAM(if without L3). 

    and I saw some points that L2 flushing was not needed.

    for ARMv8,  how can…

  • Warning: It blocks containing 32-bit Thumb instructions are deprecated in ARMv8 with GCC 4.9

    Dear colleagues.

    I am compiling the Intel TBB in an effort to optimize my code to the Cortex-M53, however, because I was still forced to use GCC 4.9 I'm getting some warning messages about the use of  32bit Thumb Instrucions in IT blocks:

    Warning…

  • Please let me know about different between "block entry" and "table entry" in VMSAv8-64 Translation table

    Hi, experts:

    What is the relationship between block and table descriptor? And, Why block descriptor is required?

    As i known, The non-ARM architecture do not have block entry for table translation walk.

    best wishes,

  • Need to know how to make an ARMV8 assembly call from C code

    Hello. I'm working on a DS-5 project for a computer architecture class.

    Our instructor set up and put the project up for download. However for our final project my group and I are to work together on a small implementation of our choice.

    Since its…

  • c-code example how to use neon ARMv8 intrinsics

    hello ,

    can you share c-code examples how to use neon ARMv8 intrinsics ?

    mostly , I'm not sure , what results to expect.

  • ARM Zynq Cortex-A53: implementing complex matrix inversion

    Hello,

    I am developing embedded software on Zynq MPSOC Cortex-A53 (Armv7/Armv8) for image processing, and I need some help for developing a specific algorithm.

    The algorithm involves many calculations of FFT and matrix using. As highest priority, we…

  • TRFCR_EL1 register

    Does anyone know the register TRFCR_EL1 in ARMv8, I can't find it in arm v8 architecture, thanks a lot.

  • XN bit in translation descriptor

    Hi all,

    I am studying ARMv8_VSMA. I have a question about the XN bit in the table descriptor.

    In the manual, there is an explanation about this as below.
    Execute-never controls determine whether instructions can be executed from a memory region.

    Here is…

  • dsb and dmb

    Hi all:

    I have some questions about DMB and DSB in armv8.

    (1)

    In armv8 Reference Manual doc, it says "The DMB instruction does not ensure the completion of any of the memory accesses for which it ensures relative order".

    But in ARM Cortex-A…

  • by which instruction the secondary core is triggered while starting the secondary cpu

    the booting of seconday cpu is initiated by the primary core. and some work is completed on the primary cpu and some is completed on the secondary cpu to complete the hotplug operation for cpu_up.

    I am trying to find the exact instruction that is executed…

  • does ARM v8 bus architecture & related IPs be compatible with v7 core?

    I would like to get some confirmation that if we replace A53/A72 with A7/A9 while the SoC architecture is still based on ARM v8 bus & IPs (e.g. CCI400, NIC400, TZC400, GIC500, BP141), does such design feasible and workable?

  • Zeroise complete L1 and L2 caches in ARM v8?

    Hi All,

    my situation is, I have to zeroize complete caches in ARM-v8 (Xilinx Ultrascale+ Device). Zeroise or set every line to constant values.

    Does anybody know how can I solve this?

    Thanks in advance.

  • PoU (Point of Unification)

    Hi all,

     

    When reading the ARMv8 reference manual, it mentions a concept of PoU. My understanding is that, if the every CPU core in a cluster has its own L1 cache, and all clusters share an L2 cache, then the PoU is L2 cache.

    1. Is my understanding is correct…