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  • Changing prio of running IRQ triggers hardfault

    Hello

    I've a question regarding the NVIC on Cortex M4 devices. Up until today I was under the impression that changing the priorities of a running interrupt isn't an issue in the ARMv7-M architecture, but the following pseudo-code snippet keeps triggering…

  • Critical interrupts

    In software there are often cases where you need to have critical interrupts serviced. For example, for:

    • Code profiling
    • Kernel debugging
    • Watchdog handling
    • Error handling.

    With the ARMv7-M architecture this can be achieved using nested interrupt handlers, but…