Hi,
I find C code not executing in the desired way. Then I step in assembly code of Tiva-C M4F core. Below is the disassembly code:
$C$L5: nop
0000033a: 280A CMP R0, #10…
According to ARM Architecture Procedure Call Standard (AAPCS) on the ARMv6-M, and ARMv7-M architecture in it says:
"Although the processor hardware allows SP to be at any word aligned address at function boundaries, standard programming practice…
Hi all,
I'm trying to understand the LDREX/STREX commands in an ARM Cortex M3 MCU to implement atomic access to various variables (the goal is to implement semaphores/mutexes or increment/decrement shared variables).
There are several ressources available…
Dear sirs,
Regarding v7m debug architecture, I have some questions after reading the v7m architecture document.
Q1: There is no mechanism to send instruction to the core for execution in debug state, is that true?
I guess the architecture uses debug return…
Hello guys,
I am trying to verify some features of ARMv7-M3 in a software simulator platform for ARM. But this simulator only support ARMv7-A ISA.
Is ARMv7-M3 instructions compatible to ARMv7-A, especially thumb instructions?
Thank you very much.
Hello All,
Good Morning!
I am working on Cortex m4.
I have read following about hard fault ,
"Bus Fault: detects memory access errors on instruction fetch, data read/write, interrupt vector fetch, and register stacking (save/restore) on interrupt (entry/exit…
I am seeing stack corruption running a Cortex M4 that seems to be related to interrupting multicycle instructions.
The interrupt occurs during a STMDB sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
The ICI bits at the time of the interrupt equal 7. This means that…
I have been reading about the exception mechanism of Cortex-M (M4 to be precise). The exception request is accepted by the processor if the current priority level of the processor is less than the incoming exception (this is one of the conditions to…
I want to communicate NXP LPC2378 (ARM7 core) to some other devices via SPI (Serial Peripheral Interface) protocol.
So how to write a C code to communicate a particular device as a Slave with Master (ARM7 controller)?
I believe that many of us are interested in the ARM Cortex-M7.
Recently, jyiu posted a status update, where I asked a couple of questions about the architecture.
A few questions on the subject was also asked in the Interview and Question Time with Joseph…
I need some indications to begin writing a program.
Write a compare routine to compare 64-bits values , using only two instructions.
Thanks for your indications !
Hi, I am new to ARMv8 architecture and while reading the v8 exception vectors I am not able to understand significance of adding SP_EL0 level vectors while SP_ELx vector set exists. What I am trying to find a use case where this is useful. I understand…
what are the minimum hardware requirements to setup wifi on arm-7 processors.
Greetings,
Sir,i am working on SWD, after Research on Break Point & Watch Point i found One Thing That There are Some Comparators will Do These Things but I am not Very Sure That How These are Work …
There's many references to Debugging a Hard Fault on Cortex-M3 & M4; eg
niallcooling's Developing a Generic Hard Fault handler for Armv7-M
also:
http://supp.iar.com/Support/?Note=23721
https://community.freescale.com/thread/306244 - which…
Hello,
I am looking to do a moving average function using DSP instructions of ARM Cortex M7. Unfortunately I couldn't find a direct example. My goal is to have variables for
- the sum
- the new value
- the oldest value
Then the algorithm is sum =…
Hello to all,
I am working on ARM Cortex-M4. Since it has 32-bit address bus, therefore I assumed that each 32-bit instruction will be allocated a physical address location in the Flash. But while reading the disassembly of the code, I got to know that…
The ARMv7-M reference manual notes there eight ITM trace enable registers called ITM_TER0 to ITM_TER7. However, core_cm7.h only has one ITM_TER register. Can you clarify? Is it an error in core_cm7.h?
Recently, I came back to digging into RTOS working principles at the lowest level on Cortex-M family processors. I understand the concept of SysTick (or other time base), SVC and PendSV as RTOS system exceptions. Though, one question is still itching…
Hey.
I read ARMv7-M Arch manual.
SHCSR register have SVCALLPENDED bit.
So that, It seem SVC is pendable.
But, 'Priority escalation' is written,
When the group priority of a pending synchronous fault or supervisor call is lower than or equal to…
I have some assembly for Cortex M4 (Arm 7M Thumb), I want to enable an interrupt that is connected to a push button on an STM32 F407. It works, but for some reason when I enable the set enable register, the clear enable register also gets set ? Is…
I have been reading through the ARM documentation on memory and instruction barriers.
I have read that the single core ARMv7-M parts do not reorder instructions, as such the DSB and ISB are not needed, is this correct?
I have also read the same about…
I have a question regarding BASEPRI, BASEPRI_MAX, and DMBs as they relate to both the V7-M and V7E-M architectures.
Let's say I have the following assembly,
// stuff mrs r0, BASEPRI msr BASEPRI_MAX, #3 // more stuff
Is it necessary to put a…
Hi
Related to ARMv7-M architecture:
I am searching through all infocenter documents but still cannot find anything and answer this question: "When an exception is taken into account?" I mean, are exceptions only serviced after the current instruction…
I use DWT in Cortex-M4 to catch instructions that write or read memory contents and the problem is it doesn't stop immediately where I expect, it stops after 2-3 instruction later than where it should and the contents of registers are overwritten…