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  • From the CPU's point of view, how does it distinguish an assembly code is an ARM code or a Thumb code?

    From the CPU's point of view, how does it distinguish an assembly code is an ARM code or a Thumb code?

    Is there some signal bit represent the code is ARM or Thumb code, this is just my guess.

  • shareable attribute in armv8

    Hi Experts,

                        I was going through the arm v8 mmu page table formation, when it's compared to arm v7 it is completely different.

    I could…

  • Cortex-A9 PMU cycle counter not always incrementing at CPU frequency?

    Hello,

    I want to benchmark my program running on Linux on an Altera Cyclone V SoC board, but it turns out that the values returned from the ARM Cortex-A9 PMU cycle counter suggest that some sort of CPU frequency scaling is active, which is confusing me…

  • Feature wise comparision for Cortex A series processors

    Hi Experts,

    Is there any document on feature wise comparison chart on the Cortex A series of processors ?

    Like,

    Cache for Cortex A8/9/52...

    MMU for cortex A8/9/52..

  • indicator for A core system timer implemented or not

    Hi ARM expert,

        In ARM V7 RM, I saw "This chapter describes the implementation of the ARM Generic Timer as an OPTIONAL extension to an ARMv7-A or ARMv7-R processor implementation.". So, I think it means that a SoC implementation…

  • How to understand SDIV instruction availability?

    Hi,

    When I read Thumb-2 instruction manual, it is not clear to me about SDIV availability. Especially I do not understand the last line "are not available in ARM state."

    Could you explain it to me?

    Thanks,

    New functionality introduced with Thumb…

  • ARM Cortex A9 flush cache

    I'm measuring worst case execution time of an application. I would like to flush L1, L2 (Instruction and Data) cache and then begin my measurements.

    Is it doable from user mode?

    Processor: ARM Cortex A9

    OS: Linaro Linux

  • ARMv7 "write buffer" issue

    Note: This was originally posted on 3rd July 2012 at http://forums.arm.com

    Hi All,

    I have a question about the "write buffer" for ARMv7 processor.

    Write buffer is explicitly described in TRM(tech reference manual) prior to ARMv6. E.g, how to enable…

  • Cortex-A8 - accessing banked registers from monitor mode

    Note: This was originally posted on 20th March 2012 at http://forums.arm.com

    Hi Group,
    I am working on a Cortex A-8 Processor (ARMv7-a architecture). I am in the monitor mode and trying to access SP of the SVC mode.

    I know two ways I can do it:

    1) Using the…

  • Attempt to set Secure Privileged Mode in armv7 A8 (using am3358 BBB silicon)?

    Hello to the ARM experts,

    I am relatively new to ARM hardware. Usually I use off the shelf systems (various Linux distros) to set up the BBB, as referent design.

    Recently, I have started to dive more deep into the armv7 A8 programming model. And I found…

  • In Arm v7 mmu, stage2 translation cannot use short descriptors. WHY?

    ARM V7 document states: "In ARMv7-A short descriptors only be used at EL0 and EL1 stage 1 translations. They cannot, therefore, be used by hypervisors or Secure monitor code."

    Why stage2/hypervisors/secure monitor cannot use short descriptors…

  • Cortex-A5 sets instr_pc to 0x00000008 after enabling MMU and using high exception vectors

    Hello Community,

    in our current ASIC project we have to replace an ARM926EJ-S with a Cortex-A5.

    In the moment we are facing the following problem in our bootloader:

    We intend to use the high exception vectors after reset (input vinithi is tied fix to '1…

  • Cortex-A7 instruction lists

    Just in case someone needs them, I made ARM and Thumb mode lists of Cortex-A7 instructions (because I didn't find them in the net).

    They are generated from ARMv7-A/R ARM with a simple AWK-script and then edited, so they may contain errors.

    The lists…

  • ARM instruction set pseudo instructions

    Does anyone know if there is a list of ARM instruction set pseudo instructions?

    Or better yet, an instruction list like PPC's, where there is a list of 'true instructions' with mnemonics and

    another list of "simplified mnemonics" (=pseudo instructions…

  • How to access the memory mapped debug registers?

    Now that the funny PABT-behaviour is found to be (probably) caused ny debug state, I'd like to exit debug state before return from PABT exception. The ARM v7-A/R ARM says that I should write RRQ to DBGDRCR, but it seems that in Cortex-A7 it's not accessible…

  • ARMV7A virtualization

    Hi,

    I am working on a hardware platform having 2 Cortex-A15 cores (with virtualization extensions). For routing IRQ's at PL2 to PL3 ( to hypervisor mode), I am setting HCR.IMO bit and it is working fine for core-0. If I set the HCR.IMO for core-1, will…

  • VMSAv8-64 -- worst-case effects of misprogramming of the Contiguous bit

    I would like to precisely understand the implications of misprogramming the Contiguous bit in VMSAv8-64 translation tables.

    I have a hypervisor running at EL2 in the AArch64 execution state, using two-stage memory translation for the guests. At some point…

  • how "Early Write Acknowledgement" is encoded on AXI AxCache ? equal to "bufferable"?

    ARMv8 introduces this new attribute of memory type. (B2.8.2)

    And also it recommends that "early write acknowledgement" attribute should be exported to interface between PE and interconnect fabric. (J4.1.1)

    However, there is no any clue about…

  • Which component will program TZASC?

    I have read in one ARM document

    The TrustZone Address Space Controller (TZASC) is an AXI component which partitions its slave address range into a number of memory regions. The TZASC can be programmed by Secure software to configure these regions as Secure…

  • Running armv7 binaries on armv8

    Hi Experts,

    I have binaries built for armv7 architecture, without rebuilding binaries can I run on armv8?. I think its possible, but wanted confirm is there any limitation?

    Thanks,

    Veeranna

  • ARMv7 CortexA9 Cache Policy - No allocate ?

    I was wondering if it would be possible to configure cache policy in the page table entry (short descriptor format) in such a way that the cache is used only if the data already exists in the cache? A kind of write-through / "no-allocate" policy?…

  • Correct usage of the NSTable bit in aarch64/armv7a LPAE

    I'm porting our armv7a-short descriptor OS to LPAE and aarch64. In the short descriptor MMU, the "NS" bit can only be found in the first level of the MMU (I'll call it the SECTION level), meaning that only a single page cannot be tagged as NS, a whole…

  • Precise abort vs synchronous abort in armv7

    I am new to arm architecture. I am reading exception handling from ARM cortex-A series programming guide. I have confusion about the technical difference between precise abort and synchronous abort or imprecise abort and synchronous abort. Are they refer…

  • ARMv7 how a program can check whether it is in secure state or not ?

    I think all is in the title.

    When in secure, reading the SCR register with MRC will succeed. But in non secure state, the MRC fails and I don't get any undef or abort.

    Is it my mistake here ? Or it can be "sensed" differently without crashing ?…

  • Non-Cacheable memory and DMA on armv7a

    Hi !

    Consider a micro-kernel (not Linux) where device drivers are userland applications (PL0).

    We would like to use DMA based device, like an Ethernet controller for example. To this mean, the micro kernel allocate some memory to the user application…