What I'm asking is ARM Architecture Reference Manual for ARMv8-A says in AArch32 there are two translation table formats:
On page G4-4726 (Issue B.b), there are various points listed that each…
Hi !
In order to call some functionality hard-coded in my board ROM (HAB from NXP i.MX6 board), I need to shut down the MMU: the ROM is not position independent. In particular, it is not always possible to map it and the devices correctly due to restriction…
ARM V7 document states: "In ARMv7-A short descriptors only be used at EL0 and EL1 stage 1 translations. They cannot, therefore, be used by hypervisors or Secure monitor code."
Why stage2/hypervisors/secure monitor cannot use short descriptors…
I'm porting our armv7a-short descriptor OS to LPAE and aarch64. In the short descriptor MMU, the "NS" bit can only be found in the first level of the MMU (I'll call it the SECTION level), meaning that only a single page cannot be tagged as NS, a whole…
When MMU is enabled, and a undefined abort exception is triggered, are we sure that the address stored in the `lr` / `elr_elx` registers is actually mapped by the MMU, or should I check that before trying to access the address ?
Best,
V.
Hello,
I have been reading and searching for some time and have learned a lot about the MPU on an ARMv7-a. I am attempting to use the Unified Region Base/Size registers to both limit memory access, but also have the "Base" value added to memory references…