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  • Memory barrier (DSB, DMB). Does they guarantee writing data on cache to memory?

    Hi Experts,

    I'm reading white paper for ARMv7 and ARMv8.

    but when i reading cache part and memory re-ordering, i have silly questions.....

    Suppose there are below instructions..

     

    Core A:

         STR R0, [Msg]

         STR R1, [Something…

  • shareable attribute in armv8

    Hi Experts,

                        I was going through the arm v8 mmu page table formation, when it's compared to arm v7 it is completely different.

    I could…

  • Cortex-A9 PMU cycle counter not always incrementing at CPU frequency?

    Hello,

    I want to benchmark my program running on Linux on an Altera Cyclone V SoC board, but it turns out that the values returned from the ARM Cortex-A9 PMU cycle counter suggest that some sort of CPU frequency scaling is active, which is confusing me…

  • Feature wise comparision for Cortex A series processors

    Hi Experts,

    Is there any document on feature wise comparison chart on the Cortex A series of processors ?

    Like,

    Cache for Cortex A8/9/52...

    MMU for cortex A8/9/52..

  • How to understand SDIV instruction availability?

    Hi,

    When I read Thumb-2 instruction manual, it is not clear to me about SDIV availability. Especially I do not understand the last line "are not available in ARM state."

    Could you explain it to me?

    Thanks,

    New functionality introduced with Thumb…

  • ARM Cortex A9 flush cache

    I'm measuring worst case execution time of an application. I would like to flush L1, L2 (Instruction and Data) cache and then begin my measurements.

    Is it doable from user mode?

    Processor: ARM Cortex A9

    OS: Linaro Linux

  • Cortex-A8 - accessing banked registers from monitor mode

    Note: This was originally posted on 20th March 2012 at http://forums.arm.com

    Hi Group,
    I am working on a Cortex A-8 Processor (ARMv7-a architecture). I am in the monitor mode and trying to access SP of the SVC mode.

    I know two ways I can do it:

    1) Using the…

  • Cortex-A5 sets instr_pc to 0x00000008 after enabling MMU and using high exception vectors

    Hello Community,

    in our current ASIC project we have to replace an ARM926EJ-S with a Cortex-A5.

    In the moment we are facing the following problem in our bootloader:

    We intend to use the high exception vectors after reset (input vinithi is tied fix to '1…

  • Cortex-A7 instruction lists

    Just in case someone needs them, I made ARM and Thumb mode lists of Cortex-A7 instructions (because I didn't find them in the net).

    They are generated from ARMv7-A/R ARM with a simple AWK-script and then edited, so they may contain errors.

    The lists…

  • ARM instruction set pseudo instructions

    Does anyone know if there is a list of ARM instruction set pseudo instructions?

    Or better yet, an instruction list like PPC's, where there is a list of 'true instructions' with mnemonics and

    another list of "simplified mnemonics" (=pseudo instructions…

  • How to access the memory mapped debug registers?

    Now that the funny PABT-behaviour is found to be (probably) caused ny debug state, I'd like to exit debug state before return from PABT exception. The ARM v7-A/R ARM says that I should write RRQ to DBGDRCR, but it seems that in Cortex-A7 it's not accessible…

  • ARMV7A virtualization

    Hi,

    I am working on a hardware platform having 2 Cortex-A15 cores (with virtualization extensions). For routing IRQ's at PL2 to PL3 ( to hypervisor mode), I am setting HCR.IMO bit and it is working fine for core-0. If I set the HCR.IMO for core-1, will…

  • ARMv7 CortexA9 Cache Policy - No allocate ?

    I was wondering if it would be possible to configure cache policy in the page table entry (short descriptor format) in such a way that the cache is used only if the data already exists in the cache? A kind of write-through / "no-allocate" policy?…

  • Precise abort vs synchronous abort in armv7

    I am new to arm architecture. I am reading exception handling from ARM cortex-A series programming guide. I have confusion about the technical difference between precise abort and synchronous abort or imprecise abort and synchronous abort. Are they refer…

  • Different performance in HYP and SVC mode ARMv7A?

    I'm doing some testing on Exynos5422 SoC which implements big.LITTLE architecture (A7 + A15), I'm running bare metal application which starts in HYP mode. I haven't returned from HYP mode by accident and then software delay which I implemented by simple…

  • Non-Cacheable memory and DMA on armv7a

    Hi !

    Consider a micro-kernel (not Linux) where device drivers are userland applications (PL0).

    We would like to use DMA based device, like an Ethernet controller for example. To this mean, the micro kernel allocate some memory to the user application…

  • Data synchronization Barrier and cache.

    Hi, everybody. I have system based on multiprocessors system with ARMv7-A. I need copy table from one point of memory to another. I use for this task DMA. Memory attribute is write-back cacheable. Before starting copy by DMA, I clean data cache by MVA…

  • How to know if a RAM is compatible with an architecture or a processor?

    I don't have much experience in building an embedded system from 0. I want to ask a general question as showed in the title through an example.

     

    I choose Cortex-A9 (ARMv7-Profile A architecture) as CPU.  Then I want to use DDR3 RAM of Alliance memory…

  • How memory mapping is done

    Hello, sorry if i posted in the wrong forum.

    I would like to know how memory mapping is done, that is to say which software/hardware component allow me to write for exemple into the address 0 of the flash memory in using the address 0x20000000 in my code…

  • Trustzone FIQ latency measurement When security extension is enabled

    Hello Guys,

    Please refer below attached image. as shown in this image i want to measure the different latencies in my Trustzone based application.

    Here is the list of measurements which i want to perform.   

    1) FIQ latency when RTOS runs and FIQ occurs …

  • Behavior for other data on a STR (ARMv7-A)

    When the following line is executed, what is the behavior with respect to the other words in the cache line?

    STR r1, [r0]

    The 4 bytes of data in r1 is written to the address in r0. But cache-lines are 32 bytes long. Assuming write-through (and ignoring…

  • Whether Armv7-A has a Write Buffer

    Hi,

    Does Armv7-A have a write buffer?

    If yes, when will the write buffer be drained and what's the purpose of write buffer?

  • Can we use PMU(Performance Measuring Unit) on Cortex A8 for calculating cycles on Simulator without hardware?

    ARMv7A family members will have PMU on the processor. Using this PMU, we can access cycle counts. Can we relay on this using the simulator?

  • I cannot write the sp register in the monitor mode

    I use a Cortex-A7 board and write start up code.

    I try to use Security Extension.

    I use `smc` instruction and make cpu mode monitor mode.

    In the monitor handler, I tried to changed stack pointer value for calling other functions.

    But after execute `ldr sp…

  • Cortex-A9: Eviction of dirty line from the region marked as Only "Inner Cacheable" from L1 cache - will if be allocated into L2?

    Hello,

    Consider following scenario:

    1. A 4 KB page starting @0x80000000 is marked as Normal Memory, Inner Cacheable, write-back, non-shareable, non-outer cacheable, L2 is inclusive cache.
    2. Now, the s/w writes to the first word in the page. Let's assume valid…