Browse By Tags

  • How get ARMv7 cache size

    Hi everybody!!

    I have a question on how get cache size on ARM v7-A, more specifically on A9 (or A7 or A15).

    In accordance with the TRM at page 1529 I get the value from CSSIDR register and I compute the cache size. More precisely, I do cache size = num…

  • Questions about Generic Timer in ARMv8

    When two clusters(Big/Little) exist in SoC, the timer can be used to support Synchronization between two clusters.

    But How to understand "Synchronization", anybody can tell me some typical application context? I am really confused......

    And, if…

  • Non-Cacheable memory and DMA on armv7a

    Hi !

    Consider a micro-kernel (not Linux) where device drivers are userland applications (PL0).

    We would like to use DMA based device, like an Ethernet controller for example. To this mean, the micro kernel allocate some memory to the user application…

  • A Walk Through the Cortex-A Mobile Roadmap

    Chinese Version中文版

    Introduction

    The ARM Cortex-A mobile application processor product line spans several generations and three main product tiers. Developers and SoC designers experienced with one or more of the newer ARM ARM Processors benefit from an…

  • High efficiency, midrange or high performance Cortex-A - What is the difference?

    A question that I am asked many times is – what is the fundamental difference between the high efficiency, mid range and the high performance application processors in the ARM Cortex family?

    The simple answer to this is – the power budget…

  • ARMv7-A - Power to the People

    Recently, I wrote an article called “Navigating the Cortex Maze” (Navigating the Cortex Maze) That was intended as an easy way-in to the ARM processor range, covering Cortex-A (architecture ARMv7-A), Cortex-R (ARMv7-R) and Cortex-M (ARMv7…