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  • 8-byte stack alignment for ARM Cortex-A9

    Hello everbody,


    as i have written before in "Compability between architecture ARMv5TE and ARMv7-A", we want to change our Platform-Processor from ARM946E-S to an ARM Cortex-A9. The next Point in our risk disclosure ist the stack alignment.

    Our…

  • Why I can't find the performance monitoring event for all Instructions count? How to get instructions event for my ARMV7 Cortex-A9 by PMU?

    Can anyone help?

  • De-merits in using Cortex A9 for single core processor

    Hi Experts,

    A8 is meant for single core and A9 is for multi-core based.

    Consider in case of SoC is build with single core of A9 and A8 how we could compare both in terms of some metrics/parameters like power/speed ?

  • code compile using -mcpu for ARM platform

    When using gcc to compile c code for ARM platform, we set object platform by using:

         -mcpu = xxxxxx

    To what extent will that affect results of compiling ?

    For example:

         -mcpu = cortex-a8

    and

         -mcpu = cortex…

  • The merit of data cache cleaning

    Hello everyone, my 1st question to the ARM community; please excuse my ignorance.  Fairly recently, I shared OCM (on-chip-memory) on Xilinx Zynq processor (which is dual ARM Cortex A9).  To pass message between the 2 cores, I followed the Xilinx example…

  • Cortex-A9/GIC: de-activate an active interrupt

    Hi

    my situation: Running an OS in normal-world which due to an (user) error enters safe state with interrupts disabled. The Hypervisor enters by an FIQ (watchdog) and should reset the normal-world.

    No the problem: If the normal-world error happens in an…

  • Dhrystone Testing on Cortex A9: disabling Prints increases the DMIPS.

    i am seeing an issue while doing Dhrystone test. i am using Dhrstone source code of version 2.1.

    when i run this source code on LINUX platform, i got DMIPS/MHz =1.6

    but there are some printing commands that prints variables used, when i disable them i got…

  • Questions about Generic Timer in ARMv8

    When two clusters(Big/Little) exist in SoC, the timer can be used to support Synchronization between two clusters.

    But How to understand "Synchronization", anybody can tell me some typical application context? I am really confused......

    And, if…

  • ARM Context ID Register & Process Context Switch

    Hi, all

    What is the content of Context ID Register of ARM Cortex A9. Is it OS that is responsible for assigning the value

    of Process ID and ASID? As far as I know, it is so in Linux. Is that the same in the other OSes?

    Is it essential to deal with ASID if…

  • Cortex-A9 PMU cycle counter not always incrementing at CPU frequency?

    Hello,

    I want to benchmark my program running on Linux on an Altera Cyclone V SoC board, but it turns out that the values returned from the ARM Cortex-A9 PMU cycle counter suggest that some sort of CPU frequency scaling is active, which is confusing me…

  • Feature wise comparision for Cortex A series processors

    Hi Experts,

    Is there any document on feature wise comparison chart on the Cortex A series of processors ?

    Like,

    Cache for Cortex A8/9/52...

    MMU for cortex A8/9/52..

  • ARM Cortex A9 flush cache

    I'm measuring worst case execution time of an application. I would like to flush L1, L2 (Instruction and Data) cache and then begin my measurements.

    Is it doable from user mode?

    Processor: ARM Cortex A9

    OS: Linaro Linux

  • ARMv7 CortexA9 Cache Policy - No allocate ?

    I was wondering if it would be possible to configure cache policy in the page table entry (short descriptor format) in such a way that the cache is used only if the data already exists in the cache? A kind of write-through / "no-allocate" policy?…

  • Non-Cacheable memory and DMA on armv7a

    Hi !

    Consider a micro-kernel (not Linux) where device drivers are userland applications (PL0).

    We would like to use DMA based device, like an Ethernet controller for example. To this mean, the micro kernel allocate some memory to the user application…

  • How to know if a RAM is compatible with an architecture or a processor?

    I don't have much experience in building an embedded system from 0. I want to ask a general question as showed in the title through an example.

     

    I choose Cortex-A9 (ARMv7-Profile A architecture) as CPU.  Then I want to use DDR3 RAM of Alliance memory…

  • Can we use PMU(Performance Measuring Unit) on Cortex A8 for calculating cycles on Simulator without hardware?

    ARMv7A family members will have PMU on the processor. Using this PMU, we can access cycle counts. Can we relay on this using the simulator?

  • Cortex-A9: Eviction of dirty line from the region marked as Only "Inner Cacheable" from L1 cache - will if be allocated into L2?

    Hello,

    Consider following scenario:

    1. A 4 KB page starting @0x80000000 is marked as Normal Memory, Inner Cacheable, write-back, non-shareable, non-outer cacheable, L2 is inclusive cache.
    2. Now, the s/w writes to the first word in the page. Let's assume valid…

  • A Walk Through the Cortex-A Mobile Roadmap

    Chinese Version中文版

    Introduction

    The ARM Cortex-A mobile application processor product line spans several generations and three main product tiers. Developers and SoC designers experienced with one or more of the newer ARM ARM Processors benefit from an…

  • High efficiency, midrange or high performance Cortex-A - What is the difference?

    A question that I am asked many times is – what is the fundamental difference between the high efficiency, mid range and the high performance application processors in the ARM Cortex family?

    The simple answer to this is – the power budget…

  • ARMv7-A - Power to the People

    Recently, I wrote an article called “Navigating the Cortex Maze” (Navigating the Cortex Maze) That was intended as an easy way-in to the ARM processor range, covering Cortex-A (architecture ARMv7-A), Cortex-R (ARMv7-R) and Cortex-M (ARMv7…